M374S6453CTS Datasheet, PDF (10/11 Pages) Samsung semiconductor – M374S6453CTS PC133/PC100 Unbuffered SDRAM DIMM

M374S6453CTS
PC133/PC100 Unbuffered DIMM
M374S6453CTS-L7C/L7A/L1H/L1L, C7C/C7A/C1H/C1L
• Organization : 64MX64
• Composition : 32MX8 *18
• Used component part # : K4S560832C-TL7C/7A/1H/1L,TC7C/7A/1H/1L
• # of rows in module : 2row
• # of banks in component : 4 banks
• Feature : 1,375 mil height & double sided component
• Refresh : 8K/64ms
• Contents :
Byte#.
Function described
Function Supported
-7C -7A -1H -1L -7C
0 # of bytes written into serial memory at module manufacturer
128bytes
1 Total # of bytes of SPD memory device
256bytes (2K-bit)
2 Fundamental memory type
SDRAM
3 # of row address on this assembly
13
4 # of column address on this assembly
10
5 # of module Rows on this assembly
2 Row
6 Data width of this assembly
72 bits
7 ...... Data width of this assembly
-
8 Voltage interface standard of this assembly
LVTTL
9 SDRAM cycle time from clock @CAS latency of 3
7.5ns 7.5ns 10ns 10ns 75h
10 SDRAM access time from clock @CAS latency of 3
5.4ns 5.4ns 6ns 6ns 54h
11 DIMM configuration type
ECC
12 Refresh rate & type
7.8us, support self refresh self
13 Primary SDRAM width
x8
14 Error checking SDRAM width
x8
15 Minimum clock delay for back-to-back random column
tCCD = 1CLK
16 SDRAM device attributes : Burst lengths supported
1, 2, 4, 8 & full page
17 SDRAM device attributes : # of banks on SDRAM device
4 banks
18 SDRAM device attributes : CAS latency
2&3
19 SDRAM device attributes : CS latency
0 CLK
20 SDRAM device attributes : Write latency
0 CLK
21 SDRAM module attributes
Non-buffered/Non-Registered &
redundant addressing
22 SDRAM device attributes : General
23 SDRAM cycle time @CAS latency of 2
24 SDRAM access time @CAS latency of 2
25 SDRAM cycle time @CAS latency of 1
26 SDRAM access time @CAS latency of 1
27 Minimum row precharge time (=tRP)
28 Minimum row active to row active delay (tRRD)
29 Minimum RAS to CAS delay (=tRCD)
30 Minimum activate precharge time (=tRAS)
31 Module Row density
32 Command and Address signal input setup time
33 Command and Address signal input hold time
34 Data signal input setup time
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
7.5ns 10ns 10ns 12ns 75h
5.4ns 6ns 6ns 7ns 54h
-
-
15ns 20ns 20ns 20ns 0Fh
15ns 15ns 20ns 20ns 0Fh
15ns 20ns 20ns 20ns 0Fh
45ns 45ns 50ns 50ns 2Dh
2 Row of 256MB
1.5ns 1.5ns 2ns 2ns 15h
0.8ns 0.8ns 1ns 1ns 08h
1.5ns 1.5ns 2ns 2ns 15h
Hex value
-7A -1H
80h
08h
04h
0Dh
0Ah
02h
48h
00h
01h
75h A0h
54h 60h
02h
82h
08h
08h
01h
8Fh
04h
06h
01h
01h
00h
0Eh
A0h A0h
60h 60h
00h
00h
14h 14h
0Fh 14h
14h 14h
2Dh 32h
40h
15h 20h
08h 10h
15h 20h
Note
-1L
1
1
A0h 2
60h
2
C0h 2
70h
2
2
2
14h
14h
14h
32h
20h
10h
20h
REV. 0.1 Sept. 2001