M368L3313DTL Datasheet, PDF (6/12 Pages) Samsung semiconductor – 256MB DDR SDRAM MODULE (32Mx64(16Mx64*2 bank) based on 16Mx8 DDR SDRAM)

M368L3313DTL
184pin Unbuffered DDR SDRAM MODULE
DDR SDRAM IDD spec table
Symbol
B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit
Notes
IDD0
IDD1
IDD2P
1320
1520
48
1200
1400
48
1200
mA
1400
mA
48
mA
IDD2F
400
352
352
mA
IDD2Q
288
240
240
mA
IDD3P
IDD3N
IDD4R
560
960
1760
560
880
1576
560
mA
880
mA
1576
mA
IDD4W
IDD5
1696
2000
1480
1880
1480
mA
1880
mA
IDD6
Normal
Low power
IDD7A
32
16
3120
32
16
2840
32
16
2840
mA
mA
Optional
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
AC OPERATING CONDITIONS
Parameter/Condition
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
VREF + 0.31
0.7
0.5*VDDQ-0.2
Max
VREF - 0.31
VDDQ+0.6
0.5*VDDQ+0.2
Unit
V
V
V
V
Note
3
3
1
2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V_IX is expected to equal 0.5*V _DDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, T A= 0 to 70 °C)
Parameter
Input reference voltage for Clock
Value
0.5 * VDDQ
Input signal maximum peak swing
1.5
Input Levels(VIH/VIL)
Input timing measurement reference level
VREF+0.31/VREF-0.31
VREF
Output timing measurement reference level
Output load condition
Vtt
See Load Circuit
Unit
V
V
V
V
V
Note
Rev. 0.2 May.2002