M368L3313DTL Datasheet, PDF (5/12 Pages) Samsung semiconductor – 256MB DDR SDRAM MODULE (32Mx64(16Mx64*2 bank) based on 16Mx8 DDR SDRAM)

M368L3313DTL
184pin Unbuffered DDR SDRAM MODULE
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
V IN, VOUT
VDD
-0.5 ~ 3.6
-1.0 ~ 3.6
Voltage on VDDQ supply relative to Vss
Storage temperature
Power dissipation
VDDQ
TSTG
PD
-1.0 ~ 3.6
-55 ~ +150
24
Short circuit current
IOS
50
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Unit
V
V
V
°C
W
mA
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to V SS=0V, T A=0 to 70°C)
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage(for device with a nominal V DD of 2.5V)
VDD
2.3
I/O Supply voltage
VDDQ
2.3
2.7
2.7
V
I/O Reference voltage
V REF
VDDQ/2-50mV VDDQ/2+50mV
V
1
I/O Termination voltage(system)
Input logic high voltage
V_TT
V REF-0.04
VR E F+ 0 . 0 4
V
2
V I H(DC)
VR E F+ 0 . 1 5
VDDQ +0.3
V
4
Input logic low voltage
Input Voltage Level, CK and CK inputs
VIL (DC)
-0.3
V REF-0.15
V
4
V I N(DC)
-0.3
VDDQ +0.3
V
Input Differential Voltage, CK and CK inputs
V I D(DC)
0.3
VDDQ +0.6
V
3
Input crossing point voltage, CK and CK inputs
VIX ( D C )
1.15
1.35
V
5
Input leakage current
II
-2
2
uA
Output leakage current
Output High Current(Normal strengh driver)
;V _OUT = V_TT + 0.84V
Output High Current(Normal strengh driver)
;V _OUT = V_TT - 0.84V
Output High Current(Half strengh driver)
;V _OUT = V_TT + 0.45V
Output High Current(Half strengh driver)
;V _OUT = V_TT - 0.45V
IO Z
-5
IOH
-16.8
IOL
16.8
IOH
-9
IOL
9
5
uA
mA
mA
mA
mA
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in V REF noise. VREF should be de-coupled with an inductance of ≤ 3nH.
2.V_TT is not applied directly to the device. V_{T T} is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.2 May.2002