K4S561633C-RL Datasheet, PDF (6/8 Pages) Samsung semiconductor – 16Mx16 SDRAM 54CSP

K4S561633C-R(B)L/N/P
CMOS SDRAM
AC OPERATING TEST CONDITIONS(VDD = 2.7V ~ 3.6V, TA =Commercial, Extended, Industrial Temperature)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4 / 0.4
0.5 x VDDQ
tr/tf = 1/1
0.5 x VDDQ
See Fig. 2
Unit
V
V
ns
V
VDDQ
Vtt = 0.5 x VDDQ
Output
870 Ω
1200 Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
30pF
Output
Z0 = 50Ω
50 Ω
30pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
- 75
-1H
-1L
Unit
Note
Row active to row active delay
tRRD (min)
15
19
19
ns
1
RAS to CAS delay
tRCD (min)
19
19
24
ns
1
Row precharge time
tRP(min)
19
19
24
ns
1
Row active time
tRAS(min)
45
50
60
ns
1
tRAS(max)
100
us
Row cycle time
tR C(min)
65
70
84
ns
1
Last data in to row precharge
tRDL(min)
2
CLK
2, 3
Last data in to Active delay
tDAL (min)
tRDL + tRP
-
3
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL (min)
1
CLK
2
Col. address to col. address delay
tCCD (min)
1
CLK
4
Number of valid output data
CAS latency=3
CAS latency=2
2
1
ea
5
CAS latency=1
-
0
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge
command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode.
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.4 Dec. 2002