K4H560438D-NC Datasheet, PDF (6/18 Pages) Samsung semiconductor – 256Mb sTSOPII

256Mb sTSOPII
DDR SDRAM
Command Truth Table
Register
Register
Refresh
COMMAND
Extended MRS
Mode Register Set
Auto Refresh
Self
Refresh
Entry
Exit
Bank Active & Row Address
Read &
Auto Precharge Disable
Column Address _{Auto Precharge Enable}
Write &
Auto Precharge Disable
Column Address _{Auto Precharge Enable}
Burst Stop
Precharge
Bank Selection
All Banks
Active Power Down
Entry
Exit
Precharge Power Down Mode
Entry
Exit
DM
No operation (NOP) : Not defined
CKEn-1 CKEn
H
X
H
X
H
H
L
L
H
H
X
H
X
H
X
H
X
H
X
H
L
L
H
H
L
L
H
H
H
X
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
CS RAS
L
L
CAS WE BA0,1 A10/AP
A11,A12
A9 ~ A0
L
L
OP CODE
Note
1, 2
L
L
L
L
OP CODE
1, 2
3
L
L
L
H
X
3
L
H
H
H
3
X
HX
X
X
3
L
L
H
H
V
L
H
L
H
V
Row Address
L
Column
4
H
Address
4
L
H
L
L
V
L
H
Column
Address
4
4, 6
L
H
H
L
X
7
V
L
L
L
H
L
X
H
X
5
HX
X
X
L
V
V
V
X
X
X
X
X
HX
X
X
L
H
H
H
X
HX
X
X
L
V
V
V
X
X
8
HX
X
X
9
X
L
H
H
H
9
1. OP Code : Operand Code. A 0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2.EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA 0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tR P after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
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Rev.0.0 May. ’02