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K4H560438D-NC Datasheet, PDF (1/18 Pages) Samsung semiconductor – 256Mb sTSOPII
256Mb sTSOPII
DDR SDRAM
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 54pin sTSOP II package
ORDERING INFORMATION
Part No.
K4H560438D-NC/LB3
K4H560438D-NC/LA2
K4H560438D-NC/LB0
K4H560438D-NC/LA0
K4H560838D-NC/LB3
K4H560838D-NC/LA2
K4H560838D-NC/LB0
K4H560838D-NC/LA0
Org.
64M x 4
32M x 8
Max Freq.
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
Interface
SSTL2
SSTL2
Operating Frequencies
Speed @CL2
Speed @CL2.5
DLL jitter
*CL : Cas Latency
- B3(DDR333)
133MHz
166MHz
±0.7ns
- A2(DDR266A)
133MHz
133MHz
±0.75ns
- B0(DDR266B)
100MHz
133MHz
±0.75ns
Package
54pin sTSOP II
54pin sTSOP II
- A0(DDR200)
100MHz
-
±0.8ns
-1 -
Rev.0.0 May. ’02