DS_K7M323625M Datasheet, PDF (6/18 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 Flow-Through NtRAM

K7M323625M
K7M321825M
1Mx36 & 2Mx18 Flow-Through NtRAM^TM
FUNCTION DESCRIPTION
The K7M323625M and K7M321825M are NtRAM^TM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of O E, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAM^TM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables( CS1, CS 2, CS 2)
are active .
Output Enable(OE ) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables( CS 1, CS2, CS2) are active, the write enable input signals WE are driven
high, and ADV driven low. Data appears at the outputs within the same clock cycle as the address for the data. Also during read
operation OE must be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW [d:a] can be used for byte write operation. The Flow
Through NtRAM^TM uses a late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required one cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
BURST SEQUENCE TABLE
LBO PIN
HIGH
First Address
Fourth Address
Case 1
A1
A0
0
0
0
1
1
0
1
1
Case 2
A1
A0
0
1
0
0
1
1
1
0
BQ TABLE
LBO PIN
LOW
First Address
Fourth Address
Case 1
A1
A0
0
0
0
1
1
0
1
1
Case 2
A1
A0
0
1
1
0
1
1
0
0
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed .
(Interleaved Burst, LBO=High)
Case 3
Case 4
A1
A0
A1
A0
1
0
1
1
1
1
1
0
0
0
0
1
0
1
0
0
(Linear Burst, LBO =Low)
Case 3
A1
A0
1
0
1
1
0
0
0
1
Case 4
A1
A0
1
1
0
0
0
1
1
0
-6-
Nov. 2003
Rev 2.0