DS_K7M323625M Datasheet, PDF (3/18 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 Flow-Through NtRAM

K7M323625M
K7M321825M
1Mx36 & 2Mx18 Flow-Through NtRAM^TM
1Mx36 & 2Mx18-Bit Flow Through NtRAM^TM
FEATURES
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A .
FAST ACCESS TIMES
Parameter
Symbol -75
Cycle Time
tCYC
8.5
Clock Access Time
tCD
7.5
Output Enable Access Time tOE
3.5
Unit
ns
ns
ns
GENERAL DESCRIPTION
The K7M323625M and K7M321825M are 37,748,736-bits Syn-
chronous Static SRAMs.
The NtRAM^TM, or No Turnaround Random Access Memory uti-
lizes all bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, Flow-Through SRAM allows output data to
simply flow freely from the memory array.
The K7M323625M and K7M321825M are implemented with
SAMSUNG′s high performance CMOS technology and is avail-
able in 100pin TQFP packages. Multiple power and ground pins
minimize ground bounce.
LOGIC BLOCK DIAGRAM
A [0:19]or
A [0:20]
LBO
A0~A1
ADDRESS
REGISTER ^{A2~A19 or A2~A20}
BURST
ADDRESS
COUNTER
A′0~A′1
CLK
K
CKE
CS 1
CS 2
CS 2
ADV
WE
BWx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb8
DQPa ~ DQPd
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
1Mx36 , 2Mx18
MEMORY
ARRAY
DATA-IN
K REGISTER
36 or 18
BUFFER
NtRAM ^TM and No Turnaround Random Access Memory are trademarks of Samsung.
-3-
Nov. 2003
Rev 2.0