DS_K7M323625M Datasheet, PDF (4/18 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 Flow-Through NtRAM

K7M323625M
K7M321825M
PIN CONFIGURATION(TOP VIEW)
1Mx36 & 2Mx18 Flow-Through NtRAM^TM
DQPc
1
D Q c0
2
D Q c1
3
VDDQ
4
VSSQ
5
D Q c2
6
D Q c3
7
D Q c4
8
D Q c5
9
VSSQ
10
VDDQ
11
D Q c6
12
D Q c7
13
Vss
14
VDD
15
VDD
16
VSS
17
DQd0
18
DQd1
19
VDDQ
20
VSSQ
21
DQd2
22
DQd3
23
DQd4
24
DQd5
25
VSSQ
26
VDDQ
27
DQd6
28
DQd7
29
DQPd
30
100 Pin TQFP
(20mm x 14mm)
K7M323625M(1Mx36)
80
DQPb
79
DQb7
78
DQb6
77
VDDQ
76
VSSQ
75
DQb5
74
DQb4
73
DQb3
72
DQb2
71
VSSQ
70
VDDQ
69
DQb1
68
DQb0
67
VSS
66
VSS
65
VDD
64
ZZ
63
DQa7
62
DQa6
61
VDDQ
60
VSSQ
59
DQa5
58
DQa4
57
DQa3
56
DQa2
55
VSSQ
54
VDDQ
53
DQa1
52
DQa0
51
DQPa
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A19
ADV
WE
CLK
CKE
CS1
CS2
CS2
B Wx(x=a,b,c,d)
OE
ZZ
LBO
Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
32,33,34,35,36,37,43
4445,46,47,48,49,50,
81,82,83,84,99,100
85
88
89
87
98
97
92
93,94,95,96
86
64
31
VDD
VSS
N.C.
D Q a0~a7
D Q b0~b7
DQc0~ c7
D Q d0~d7
DQPa~Pd
VDDQ
VSSQ
Power Supply(+3.3V) 15,16,41,65,91
Ground
14,17,40,66,67,90
No Connect
38,39,42
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
Output Ground
5,10,21,26,55,60,71,76
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-4-
Nov. 2003
Rev 2.0