K4H560438E-GCCC Datasheet, PDF (4/18 Pages) Samsung semiconductor – 256Mb E-die DDR 400 SDRAM Specification 60Ball FBGA (x4/x8)

DDR SDRAM 256Mb E-die (x4, x8)
Ball Description (Bottom View)
DDR SDRAM
64M x 4bit
1 VSSQ NC NC NC NC VREF
2
NC VDDQ VSSQ VDDQ VSSQ VSS CK
3
VSS DQ3 NC DQ2 DQS DM
CK
A
B
C
D
E
F
G
7
VDD DQ0 NC DQ1 NC
NC WE
8
NC VSSQ VDDQ VSSQ VDDQ VDD CAS
9 VDDQ NC NC NC NC NC
A12
CKE
H
RAS
CS
A11 A8
A6
A9
A7
A5
J
K
L
BA1 A0
A2
BA0 A10/AP A1
A4
VSS
M
VDD
A3
32M x 8bit
1 VSSQ NC NC NC NC VREF
2
DQ7 VDDQ VSSQ VDDQ VSSQ VSS CK
3
VSS DQ6 DQ5 DQ4 DQS DM
CK
A
B
C
D
E
F
G
7
VDD DQ1 DQ2 DQ3 NC
NC WE
8
DQ0 VSSQ VDDQ VSSQ VDDQ VDD CAS
9 VDDQ NC NC NC NC NC
A12
CKE
H
RAS
CS
A11 A8
A6
A9
A7
A5
J
K
L
BA1 A0
A2
BA0 A10/AP A1
A4
VSS
M
VDD
A3
Organization
64Mx4
32Mx8
Row Address
A0~A12
A0~A12
Column Address
A0-A9, A11
A0-A9
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.1 September. 2003