S3C4510B Datasheet, PDF(38/422 Page) Samsung semiconductor – Samsungs S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems.

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S3C4510B Datasheet, PDF (38/422 Pages) Samsung semiconductor – Samsungs S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems.

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PROGRAMMER'S MODEL

S3C4510B

Exception Entry/Exit Summary

Table 2-2 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended

instruction for exiting the exception handler.

Table 2-2. Exception Entry/Exit

BL

SWI

UDEF

FIQ

IRQ

PABT

DABT

RESET

Return Instruction

MOV PC, R14

MOVS PC, R14_svc

MOVS PC, R14_und

SUBS PC, R14_fiq, #4

SUBS PC, R14_irq, #4

SUBS PC, R14_abt, #4

SUBS PC, R14_abt, #8

NA

Previous State

ARM R14_x

THUMB R14_x

PC + 4

PC + 2

PC + 4

PC + 2

PC + 4

PC + 2

PC + 4

PC + 8

â

NOTES:

1. Where PC is the address of the BL/SWI/Undefined Instruction fetch which had the prefetch abort.

2. Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority.

3. Where PC is the address of the Load or Store instruction which generated the data abort.

4. The value saved in R14_svc upon reset is unpredictable.

Notes

1

2

1

3

4

FIQ

The FIQ (Fast Interrupt Request) exception is designed to support a data transfer or channel process, and in

ARM state has sufficient private registers to remove the need for register saving (thus minimizing the overhead

of context switching).

FIQ is externally generated by taking the nFIQ input LOW. This input can except either synchronous or

asynchronous transitions, depending on the state of the ISYNC input signal. When ISYNC is LOW, nFIQ and

nIRQ are considered asynchronous, and a cycle delay for synchronization is incurred before the interrupt can

affect the processor flow.

Irrespective of whether the exception was entered from ARM or Thumb state, a FIQ handler should leave the

interrupt by executing

SUBS

PC,R14_fiq,#4

FIQ may be disabled by setting the CPSR's F flag (but note that this is not possible from User mode). If the F flag

is clear, ARM7TDMI checks for a LOW level on the output of the FIQ synchroniser at the end of each instruction.

2-12

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