S3C4510B Datasheet, PDF (217/422 Pages) Samsung semiconductor – Samsungs S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems.

S3C4510B
I²C BUS CONTROLLER
I²C-Bus Addressing
The addressing procedure for the I²C-bus is such that the first byte after the start condition determines which
slave the master will select. Usually, this first byte immediately follows the start procedure.
An exception is the "general call" address which can address all ICs simultaneously. When this address is used,
all ICs should, in theory, respond with an acknowledge. However, ICs can also be made to ignore this address.
The second byte of the general call address then defines the action to be taken.
Definition of Bits in the First Data Byte
The first seven bits of the first data byte make up the slave address. The eighth bit is the LSB, or direction bit,
which determines the direction (R/W) of the message.
When an address is sent, each IC on the bus compares the first 7 bits received following start condition with its
own address. If the addresses match, the IC considers itself addressed by the master as a slave receiver or a
slave transmitter.
General Call Address
The general call address can be used to address every IC that connected to the I²C-bus. However, if an IC does
not need any of the data supplied within the general call structure, it can ignore this address by not
acknowledging it.
If an IC does require data from a general call address, it can then acknowledge this address and behave as a
slave receiver. The second and following bytes will be acknowledged by every slave receiver capable of handling
this data. A slave which cannot process one of these bytes must ignore it by not acknowledging. The meaning of
the general call address is always specified in the second byte.
Start Byte
Every data transfer is preceded by a start procedure:
— A start condition, S
— A start byte, "00000001"
— An acknowledge (ACK) clock pulse, and
— A repeated start condition, Sr
After the start condition (S) has been transmitted by a master which requires bus access, the start byte
("00000001") is transmitted. Another IC can therefore sample the SDA line at a low sampling rate until one of the
seven zeros in the start byte is detected. After it detects this low level on the SDA line, the IC can switch to a
higher sampling rate to find the repeated start condition (Sr) which is then used for synchronization. (A) hardware
receiver will reset upon receipt of the repeated start condition (Sr) and will therefore ignore the start byte.)
An acknowledge-related clock pulse is generated after the start byte. This is done only to conform with the byte
handling format used on the bus. No IC is allowed to acknowledge the start byte.
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