K9W4G08U1M Datasheet, PDF (37/40 Pages) Samsung semiconductor – 256M x 8 Bit / 128M x 16 Bit NAND Flash Memory

K9W4G08U1M K9W4G16U1M
K9K2G08Q0M K9K2G16Q0M
K9K2G08U0M K9K2G16U0M
FLASH MEMORY
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, 44h respectively.
The command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.
Figure 14. Read ID Operation
CLE
CE
tCLR
tCEA
WE
tAR1
ALE
RE
I/OX
90h
tWHR _tREA
Device
00h
ECh
Code*
XXh
Address. 1cycle
Maker code Device code
Device
K9K2G08Q0M
K9K2G08U0M
K9K2G16Q0M
K9K2G16U0M
K9W4G08U1M
K9W4G16U1M
Device Code*(2nd Cycle)
4th Cycle*
AAh
15h
DAh
15h
BAh
55h
CAh
55h
Same as each K9K2G08U0M in it
Same as each K9K2G16U0M in it
4th Cyc.*
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will be accepted by the command register. The R/B pin transitions to low for tRST after
the Reset command is written. Refer to Figure 15 below.
Figure 15. RESET Operation
tRST
R/B
I/OX
FFh
Table3. Device Status
PRE status
Operation Mode
After Power-up
High
Low
First page data access is ready
00h command is latched
After Reset
Waiting for next command
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