K4H280438F-UC Datasheet, PDF (3/23 Pages) Samsung semiconductor – 128Mb F-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant)

DDR SDRAM 128Mb F-die (x4, x8)
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 15.6us refresh interval(4K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II Pb-Free package
• RoHS compliant
DDR SDRAM
Ordering Information
Part No.
K4H280438F-UC/LA2
K4H280438F-UC/LB0
K4H280438F-UC/LA0
K4H280838F-UC/LB3
K4H280838F-UC/LA2
K4H280838F-UC/LB0
Org.
32M x 4
16M x 8
Max Freq.
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Interface
SSTL2
SSTL2
Package
66pin TSOP II
66pin TSOP II
Operating Frequencies
Speed @CL2
Speed @CL2.5
B3(DDR333@CL=2.5)
133MHz
166MHz
A2(DDR266@CL=2.0)
133MHz
133MHz
B0(DDR266@CL=2.5)
100MHz
133MHz
A0(DDR200@CL=2.0)
100MHz
-
*CL : CAS Latency
Rev. 1.1 May. 2004