K4H280438F-UC Datasheet, PDF (16/23 Pages) Samsung semiconductor – 128Mb F-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant)

DDR SDRAM 128Mb F-die (x4, x8)
DDR SDRAM
Parameter
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
B3
A2
B0
A0
Symbol ^{(DDR333@CL=2.5)) (DDR266@CL=2.0) (DDR266@CL=2.5)) (DDR200@CL=2.0))} Unit Note
Min Max Min Max Min Max Min Max
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
ns 11
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tQHS
0.55
0.75
0.75
0.8
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
ns 10, 11
ns 11
tCK 2
tRAP
18
20
20
20
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK 13
AC Operating Test Conditions
(VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Input reference voltage for Clock
Input signal maximum peak swing
Input signal minimum slew rate (for imput only)
Input slew rate (I/O pins)
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Value
0.5 * VDDQ
1.5
0.5
0.5
VREF+0.31/VREF-0.31
VREF
Vtt
See Load Circuit
AC operating test conditions
Vtt=0.5*VDDQ
Output
RT=50Ω
Z0=50Ω
CLOAD=30pF
VREF
=0.5*VDDQ
Output Load Circuit (SSTL_2)
Unit
V
V
V/ns
V/ns
V
V
V
Note
Rev. 1.1 May. 2004