K4H280438F-UC Datasheet, PDF (15/23 Pages) Samsung semiconductor – 128Mb F-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant)

DDR SDRAM 128Mb F-die (x4, x8)
DDR SDRAM
AC Timming Parameters & Specifications
Parameter
B3
A2
B0
A0
Symbol ^{(DDR333@CL=2.5 (DDR266@CL=2.0 (DDR266@CL=2.5 (DDR200@CL=2.0} Unit Note
Min Max Min Max Min Max Min Max
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
CL=2.0
CL=2.5
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time(fast)
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
tCCD
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tDSC
tIS
60
72
42
18
18
12
15
1
1
7.5
6
0.45
0.45
-0.6
-0.7
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.75
70K
12
12
0.55
0.55
+0.6
+0.7
0.45
1.1
0.6
1.25
1.1
65
65
70
75
75
80
45
120K
45
120K
48
20
20
20
20
20
20
15
15
15
15
15
15
1
1
1
1
1
1
7.5
12
10
12
10
7.5
12
7.5
12
0.45 0.55 0.45 0.55 0.45
0.45 0.55 0.45 0.55 0.45
-0.75 +0.75 -0.75 +0.75 -0.8
-0.75 +0.75 -0.75 +0.75 -0.8
-
0.5
-
0.5
-
0.9
1.1
0.9
1.1
0.9
0.4
0.6
0.4
0.6
0.4
0.75 1.25 0.75 1.25 0.75
0
0
0
0.25
0.25
0.25
0.2
0.2
0.2
0.2
0.2
0.2
0.35
0.35
0.35
0.35
0.35
0.35
0.9
1.1
0.9
1.1
0.9
0.9
0.9
1.1
120K
12
0.55
0.55
+0.8
+0.8
0.6
1.1
0.6
1.25
1.1
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
ns
tCK
tCK
ns
ns
ns 12
tCK
tCK
tCK
ns 3
tCK
tCK
tCK
tCK
tCK
tCK
ns ^i,5.7
Address and Control Input hold time(fast)
tIH
0.75
0.9
0.9
1.1
ns ^i,5.7
Address and Control Input setup time(slow)
tIS
0.8
1.0
1.0
1.1
ns ^i,
Address and Control Input hold time(slow)
tIH
0.8
1.0
1.0
1.1
ns ^i,
Data-out high impedence time from CK/CK
tHZ
+0.7
+0.75
+0.75 -0.8
+0.8 ns 1
Data-out low impedence time from CK/CK
tLZ
-0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 1
Mode register set cycle time
tMRD
12
15
15
16
ns
DQ & DM setup time to DQS
tDS
0.45
0.5
0.5
0.6
ns j, k
DQ & DM hold time to DQS
tDH
0.45
0.5
0.5
0.6
ns _{j, k}
Control & Address input pulse width
tIPW
2.2
2.2
2.2
2.5
ns 8
DQ & DM input pulse width
tDIPW 1.75
1.75
1.75
2
ns 8
Power down exit time
tPDEX
6
7.5
7.5
10
ns
Exit self refresh to non-Read command
tXSNR
75
75
75
80
ns
Exit self refresh to read command
tXSRD 200
200
200
200
tCK
Refresh interval time
tREFI
7.8
7.8
7.8
15.6
us 4
Output Slew Rate Matching Ratio(rise to fall) tSLMR 0.67
1.5
0.67
1.5
0.67
1.5
0.67
1.5
Rev. 1.1 May. 2004