K4D553238F Datasheet, PDF (3/17 Pages) Samsung semiconductor – 256Mbit GDDR SDRAM

K4D553238F-GC
256M GDDR SDRAM
2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• 2.5V ± 5% power supply for device operation
• 2.5V ± 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 4, 5 and 6 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 4 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA
• Maximum clock frequency up to 350MHz
• Maximum data rate up to 700Mbps/pin
ORDERING INFORMATION
Part NO.
K4D553238F-GC2A
K4D553238F-GC33
K4D553238F-GC36
Max Freq.
350MHz
300MHz
275MHz
* K4D553238F-VC is the Lead Free package part number.
Max Data Rate
700Mbps/pin
600Mbps/pin
550Mbps/pin
Interface
SSTL_2
Package
144-Ball FBGA
GENERAL DESCRIPTION
FOR 2M x 32Bit x 4 Bank DDR SDRAM
The K4D553238F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by
32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 2.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
-3-
Rev 1.3 (Mar. 2005)