K4D553238F Datasheet, PDF (13/17 Pages) Samsung semiconductor – 256Mbit GDDR SDRAM

K4D553238F-GC
AC CHARACTERISTICS
Parameter
CK cycle time
CL=3
CL=4
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
Clock half period
Data Hold skew factor
Data output hold time from DQS
Jitter over 1~6 clock cycle error
Cycle to cyde duty cycle error
Rise and fall times of CK
Symbol
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
tIH
tDS
tDH
tHP
tQHS
tQH
tJ*1
tDCERR
tR, tF
-2A
Min
Max
-
4
2.86
0.45
0.55
0.45
0.55
-0.55
0.55
-0.55
0.55
-
0.35
0.9
1.1
0.4
0.6
0.85
1.15
0
-
0.35
-
0.4
0.6
0.45
0.55
0.45
0.55
0.8
-
0.8
-
0.35
-
0.35
-
tCLmin
or
-
tCHmin
-
0.4
tHP-tQHS
-
-
75
-
75
-
600
*1. The cycle to cycle jitter over 1~6 cycle short term jitter.
256M GDDR SDRAM
-33
Min
Max
-
10
3.3
0.45
0.55
0.45
0.55
-0.55
0.55
-0.55
0.55
-
0.35
0.9
1.1
0.4
0.6
0.85
1.15
0
-
0.35
-
0.4
0.6
0.45
0.55
0.45
0.55
0.8
-
0.8
-
0.35
-
0.35
-
tCLmin
or
-
tCHmin
-
0.4
tHP-tQHS
-
-
85
-
85
-
700
-36
Min
Max
-
10
3.6
0.45
0.55
0.45
0.55
-0.6
0.6
-0.6
0.6
-
0.40
0.9
1.1
0.4
0.6
0.85
1.15
0
-
0.35
-
0.4
0.6
0.45
0.55
0.45
0.55
0.9
-
0.9
-
0.40
-
0.40
-
tCLmin
or
-
tCHmin
-
0.45
tHP-tQHS
-
-
95
-
95
-
700
Unit Note
ns
ns
tCK
tCK
ns
ns
ns
1
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
1
ns
ns
1
ps
ps
ps
Simplified Timing @ BL=2, CL=4
0
1
CK, CK
tCH
tCL
tCK
2
3
4
5
CS
DQS
DQ
DM
COMMAND _READA
tRPRE
tDQSCK
tRPST
tDQSQ
tAC
Qa1 Qa2
6
7
8
tIS
tIH
tDQSS
tWPREH
tDQSH
tDQSL
tWPRES
tDS tDH
Db0 Db1
WRITEB
- 13 -
Rev 1.3 (Mar. 2005)