S6A0075 Datasheet, PDF (24/70 Pages) Samsung semiconductor – 100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Table 6. Instruction Set 1 (Continued)
Instruction Code
Instruction RE
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
Executio
n Time
(fosc =
270kHz)
Function
set
Set interface data length
(DL = "1": 8-bit, DL = "0": 4-bit),
numbers of display line when
NW = "0", (N = "1": 2-line, N = "0" :
0
0
0
0
0
RE
1-line), extension register, RE("0"),
1 DL N ₍₀₎ DH REV _{shift/scroll enable}
39µs
DH = "1": display shift enable
DH = "0": dot scroll enable. reverse
bit REV = "1": reverse display,
REV = "0": normal display.
Set DL, N, RE("1") and
1
0
0
0
0
1
DL
N
RE
(1)
BE
0
CGRAM/SEGRAM blink enable
BE)
BE = " 1/0": CGRAM/SEGRAM
blink enable/disable
39µs
Set
CGRAM
address
0
0
0
0
1
AC5
AC4
AC3
AC2 AC1
AC0
Set CGRAM address in address
counter.
39µs
Set
SEGRAM
1
0
0
0
1
X
X
AC3
AC2 AC1
AC0
Set SEGRAM address in address
counter.
address
39µs
Set
DDRAM
address
0
0
0
1
AC6
AC5
AC4
AC3
AC2 AC1
AC0
Set DDRAM address in address
counter.
39µs
Set scroll
quantity
10
0
1
X
QC QC QC QC QC QC
543210
Set the quantity of horizontal dot
scroll.
39µs
Can be known whether during
Read busy
internal operation or not by
flag and
address
X0
1
BF
AC6 AC5 AC4 AC3 AC2 AC1 AC0
reading BF. The contents of
address counter can also be read.
BF = "1": busy state
0µs
BF = "0": ready state
Write data X 1
Write data into internal RAM
0 D7 D6 D5 D4 D3 D2 D1 D0 _{(DDRAM / CGRAM / SEGRAM).}
43µs
Read data X 1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data from internal RAM
(DDRAM / CGRAM / SEGRAM).
43µs
NOTES:
1. When an MPU program with busy flag (DB7) checking is made, 1/2 fosc (is necessary) for executing the next instruction
by the "E" signal after the busy flag (DB7) goes to "Low"
2. "X": Don’t care
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