S3C4530A Datasheet, PDF (17/432 Pages) Samsung semiconductor – 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller

S3C4530A
PRODUCT OVERVIEW
Table 1-3. S3C4530A PAD Type
Pad
Type
ptic
ptis
pticu
pticd
pia_bb
pob1
ptot2
pob4
ptot4
ptot6
ptbsut1
ptbcut4
ptbcd4
ptbst4sm
ptbsut6
I/O
Type
I
I
I
I
I
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
Current
Drive
Cell Type
Feature
-
-
-
-
-
1mA
2mA
4mA
4mA
6mA
1mA
4mA
4mA
4mA
6mA
LVCMOS Level
5V-tolerant
LVCMOS Schmit Trigger Level
5V-tolerant
LVCMOS Level
5V-tolerant
Pull-up register
LVCMOS Level
5V-tolerant
Pull-down register
Analog input with separate bulk bias -
Normal Buffer
-
Tri-state Buffer
5V-tolerant
Normal Buffer
-
Tri-state Buffer
5V-tolerant
Tri-state Buffer
5V-tolerant
LVCMOS Schmit trigger level Tri- 5V-tolerant Pull-up
state Buffer
register
LVCMOS Level Tri-state Buffer
5V-tolerant
LVCMOS Level Open drain Buffer 5V-tolerant
LVCMOS Schmit trigger level
5V-tolerant
LVCMOS Schmit trigger level
5V-tolerant
pull-up register
Slew-Rate
Control
-
-
-
-
-
-
-
-
-
-
-
Medium
-
Medium
-
NOTE: pticu and pticd provides 100K Ohm Pull-up(down) register. For detail information about the pad type,
see Chapter 4. Input/Output Cells of the "STD90/MDL90 0.35um 3.3V Standard Cell Library Data Book",
produced by Samsung Electronics Co., Ltd, ASIC Team
nRESET
64*fMCLK
512*fMCLK
nRSCO
NOTE: After the falling edge of nRESET, the S3C4530A count 64 cycles for a system reset
and needs further 512 cycles for a TAG RAM clear of cache.
After these cycles, the S3C4530A asserts nRCS0 when the nRESET is released.
Figure 1-3. Reset Timing Diagram
1-17