S3C4530A Datasheet, PDF (161/432 Pages) Samsung semiconductor – 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller

S3C4530A
SYSTEM MANAGER
Start Address Setting
The start address of the System Manager special register area is initialized to 4FFFFF91H. (You can also set the
start address to an arbitrary value, for example 3FF0000H.) When you have set the start address of the special
register area, the register addresses are automatically defined as the start address plus the register’s offset.
Assume for example, that a reset initializes the start address to 3FF0000H. The offset address of the ROMCON
register is 3014H. Therefore, the physical address for ROMCON is 3FF0000H + 3014H = 3FF3014H. If you
modified the start address of the special register area to 3000000H, the new address for the ROMCON register
would be 3003014H.
Cache Disable/Enable
To enable or disable the cache, you set the cache enable (CE) bit of the SYSCFG register to "1" or "0",
respectively. Because cache memory does not have an auto-flush feature, you must be careful to verify the
coherency of data whenever you re-enable the cache. You must also carefully check any changes that the DMA
controller may make to data stored in memory. (Usually, the memory area that is allocated to DMA access
operations must be non-cacheable.)
The internal 8-Kbyte SRAM can be used as a cache area. To configure this area, you use the cache mode bits,
SYSCFG[5:4]. If you do not need to use the entire 8-Kbyte area as cache, you can use the remaining area as
internal SRAM. This area is accessed using the address of the base pointer in the internal SRAM field.
Write Buffer Disable/Enable
The S3C4530A has four programmable write buffer registers that are used to improve the speed of memory write
operations. When you enable a write buffer, the CPU writes data into the write buffer, instead of an external
memory location. This saves the cycle that would normally be required to complete the external memory write
operation. The four write buffers also enhance the performance of the ARM7TDMI core’s store operations.
To maintain data coherency between the cache and external memory, the S3C4530A uses a write-through policy.
An internal 4-level write buffer compensates for performance degradation caused by write-through.
(For more information, see Chapter 5.)
Stall Disable/Enable
Stall Enable bit is used when the CPU accesses data under non-sequential mode and the system clock is too fast
to decode the local address within the given time.
When the stall option is enabled, the CPU core logic inserts a wait about non-sequential memory access
occurred. So, the CPU core has more time margin. When the stall bit disabled, the logic does not insert a wait.
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