S3C4530A Datasheet, PDF (15/432 Pages) Samsung semiconductor – 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller

S3C4530A
PRODUCT OVERVIEW
Group
Ethernet
Controller
(18)
HDLC
Channel A
(9)
HDLC
Channel B
(9)
Table 1-2. S3C4530A Pin List and PAD Type (Continued)
Pin Name
MDC
MDIO
COL/ COL_10M
TX_CLK/ TXCLK_10M
TXD[3:0]/TXD_10M
TX_EN/ TXEN_10M
TX_ERR/ PCOMP_10M
CRS/ CRS_10M
RX_CLK/ RXCLK_10M
RXD[3:0]/ RXD_10M
RX_DV/ LINK_10M
RX_ERR
TXDA
RXDA
nDTRA
nRTSA
nCTSA
nDCDA
nSYNCA
RXCA
TXCA
TXDB
RXDB
nDTRB
nRTSB
nCTSB
nDCDB
nSYNCB
RXCB
TXCB
Pin
Counts
1
1
1
1
4
1
1
1
1
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I/O Pad
Type Type
Description
O pob4 Management data clock.
I/O ptbcut4 Management data I/O.
I ptis
Collision detected/collision detected for
10M.
I ptis Transmit data/transmit data for 10M.
O pob4 Transmit data/transmit data for 10M.
O pob4 Transmit enable or transmit enable for
10M.
O pob4 Transmit error/packet compression
enable for 10M.
I ptis Carrier sense/carrier sense for 10M.
I ptis Receive clock/receive clock for 10M.
I ptis Receive data/receive data for 10M.
I ptis Receive data valid.
I ptis Receive error.
O pob4 HDLC channel A transmit data.
I ptis HDLC channel A receive data.
O pob4 HDLC channel A data terminal ready.
O pob4 HDLC channel A request to send.
I ptis HDLC channel A clear to send.
I ptis HDLC channel A data carrier detected.
O pob4 HDLC channel A sync is detected.
I ptis HDLC channel A receiver clock.
I/O ptbsut1 HDLC channel A transmitter clock.
O pob4 HDLC channel B transmit data.
I ptis HDLC channel B receive data.
O pob4 HDLC channel B data terminal ready.
O pob4 HDLC channel B request to send.
I ptis HDLC channel B clear to send.
I ptis HDLC channel B data carrier detected.
O pob4 HDLC channel B sync is detected.
I ptis HDLC channel B receiver clock.
I/O ptbsut1 HDLC channel B transmitter clock.
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