K4H561638H Datasheet, PDF (16/24 Pages) Samsung semiconductor – 256Mb H-die DDR SDRAM Specification

K4H561638H
Only for Aisin-AW
Preliminary
Industrial DDR SDRAM
19.0 AC Timming Parameters & Specifications
Parameter
Symbol
Row cycle time
tRC
Refresh row cycle time
tRFC
Row active time
tRAS
RAS to CAS delay
tRCD
Row precharge time
tRP
Row active to Row active delay
tRRD
Write recovery time
tWR
Last data in to Read command
tWTR
CL=2.0
Clock cycle time
CL=2.5 tCK
CL=3.0
Clock high level width
tCH
Clock low level width
tCL
DQS-out access time from CK/CK
tDQSCK
Output data access time from CK/CK
tAC
Data strobe edge to
ouput data edge
TSOP Package ^tDQSQ
FBGA Package tDQSQ
Read Preamble
tRPRE
Read Postamble
tRPST
CK to valid DQS-in
tDQSS
DQS-in setup time
tWPRES
DQS-in hold time
tWPRE
DQS falling edge to CK rising-setup time tDSS
DQS falling edge from CK rising-hold time tDSH
DQS-in high level width
tDQSH
DQS-in low level width
tDQSL
Address and Control Input setup time(fast) tIS
Address and Control Input hold time(fast)
tIH
Address and Control Input setup
tIS
CC
(DDR400@CL=3.0)
Min
55
70
40
15
15
10
15
2
-
6
5
0.45
0.45
-0.55
-0.65
-
-
0.9
0.4
0.72
0
0.25
0.2
0.2
0.35
0.35
0.6
0.6
Max
70K
-
12
10
0.55
0.55
+0.55
+0.65
0.4
-
1.1
0.6
1.28
0.7
B3
(DDR333@CL=2.5)
Min
Max
60
72
42
70K
18
18
12
15
1
7.5
12
6
12
-
-
0.45
0.55
0.45
0.55
-0.6
+0.6
-0.7
+0.7
-
0.45
-
0.4
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.2
0.2
0.35
0.35
0.75
0.75
0.8
Address and Control Input hold time(slow) tIH
0.7
0.8
Data-out high impedence time from CK/CK tHZ
-0.65
+0.65
-0.7
Data-out low impedence time from CK/CK tLZ
-0.65
+0.65
-0.7
Mode register set cycle time
tMRD
10
12
DQ & DM setup time to DQS
tDS
0.4
0.45
+0.7
+0.7
DQ & DM hold time to DQS
tDH
0.4
0.45
Control & Address input pulse width
tIPW
2.2
2.2
DQ & DM input pulse width
tDIPW
1.75
1.75
Exit self refresh to non-Read command
tXSNR
75
75
Exit self refresh to read command
tXSRD
200
200
Refresh interval time
Output DQS valid window
tREFI
7.8
7.8
tHP
tQH
-tQHS
-
tHP
-tQHS
-
Clock half period
tCLmin
tHP
or tCHmin
-
tCLmin
or tCHmin
-
Data hold skew factor TSOP Package ^tQHS
0.5
0.55
FBGA Package _tQHS
-
-
0.5
DQS write postamble time
tWPST
0.4
0.6
0.4
0.6
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
tRAP
tDAL
15
(tWR/tCK)
+
(tRP/tCK)
18
(tWR/tCK)
+
(tRP/tCK)
Power Down Exit Time
tPDEX
1
1
B0
(DDR266@CL=2.5)
Min
65
75
45
20
20
15
15
1
10
7.5
-
0.45
0.45
-0.75
-0.75
-
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
Max
70K
12
12
-
0.55
0.55
+0.75
+0.75
0.5
0.5
1.1
0.6
1.25
1.0
1.0
-0.75
-0.75
15
0.5
+0.75
+0.75
0.5
2.2
1.75
75
200
7.8
tHP
-tQHS
-
tCLmin
or tCHmin
-
0.75
0.75
0.4
0.6
20
(tWR/tCK)
+
(tRP/tCK)
1
Unit Note
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
tCK
tCK
ns
ns
ns 22
tCK
tCK
tCK
ns 13
tCK
tCK
tCK
tCK
tCK
ns 15, 17~19
ns 15, 17~19
ns 16~19
ns 16~19
ns 11
ns 11
ns
ns j, k
ns _{j, k}
ns 18
ns 18
ns
tCK
us 14
ns 21
ns 20, 21
ns 21
tCK 12
tCK 23
tCK
Rev. 1.2 January 2006