K4D263238M Datasheet, PDF (14/19 Pages) Samsung semiconductor – 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL

K4D263238M
128M DDR SDRAM
AC CHARACTERISTICS
Parameter
Symbol
CK cycle time
CL=3
CL=4
tCK
CK high level width
tCH
CK low level width
tCL
DQS out access time from CK tDQSCK
Output access time from CK tAC
Data strobe edge to Dout edge tDQSQ
Read preamble
tRPRE
Read postamble
tRPST
CK to valid DQS-in
tDQSS
DQS-In setup time
tWPRES
DQS-in hold time
tWPREH
DQS write postamble
tWPST
DQS-In high level width
tDQSH
DQS-In low level width
tDQSL
Address and Control input
setup
tIS
Address and Control input hold tIH
DQ and DM setup time to DQS tDS
DQ and DM hold time to DQS tDH
Clock half period
tHP
Data output hold time from
DQS
tQH
-45*
Min
Max
-
10
4.5
0.45
0.55
0.45
0.55
-0.7
+0.7
-0.7
+0.7
-
+0.45
0.9
1.1
0.4
0.6
0.8
1.2
0
-
0.25
-
0.4
0.6
0.4
0.6
0.4
0.6
1.0
-
1.0
-
0.45
-
0.45
-
tCLmin
or
-
tCHmin
tHP-0.45
-
-50
Min
Max
5.0
10
0.45
0.55
0.45
0.55
-0.7
+0.7
-0.7
+0.7
-
+0.45
0.9
1.1
0.4
0.6
0.8
1.2
0
-
0.25
-
0.4
0.6
0.4
0.6
0.4
0.6
1.0
-
1.0
-
0.45
-
0.45
-
tCLmin
or
-
tCHmin
tHP-0.45
-
-55
Min
Max
5.5
10
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.4
0.4
0.4
0.55
0.55
+0.75
+0.75
+0.5
1.1
0.6
1.25
-
-
0.6
0.6
0.6
1.1
-
1.1
-
0.5
-
0.5
-
tCLmin
or
-
tCHmin
tHP-0.5
-
-60
Min
Max
6.0
10
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.4
0.4
0.4
0.55
0.55
+0.75
+0.75
+0.5
1.1
0.6
1.25
-
-
0.6
0.6
0.6
1.1
-
1.1
-
0.5
-
0.5
-
tCLmin
or
-
tCHmin
tHP-0.5
-
Unit Note
ns
ns
tCK
tCK
ns
ns
ns
1
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
1
ns
1
Simplified Timing @ BL=2, CL=3
0
1
CK, CK
CS
DQS
DQ
DM
COMMAND READA
tCH
tCL
tCK
2
3
4
5
6
7
tRPRE
tDQSCK
tRPST
tDQSQ
tAC
Da1 Da2
tIS
tIH
tDQSS
tWPREH
tDQSH
tWPST
tWPRES
tDS tDH
Db0 Db1
WRITEB
8
Hi-Z
Hi-Z
- 14 -
Rev. 1.3 (Aug. 2001)