M366S3354BTS Datasheet, PDF (13/22 Pages) Samsung semiconductor – SDRAM Unbuffered Module 168pin Unbuffered Module based on 512Mb B-die 62/72-bit Non ECC/ECC

256MB, 512MB, 1GB Unbuffered DIMM
DC CHARACTERISTICS
M374S6553ETS (64M x 72, 512MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating current
(One bank active)
Precharge standby current
in power-down mode
Precharge standby current
in non power-down mode
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
Operating current
(Burst mode)
Refresh current
Self refresh current
Symbol
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
ICC5
ICC6
Test Condition
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
tRC ≥ tRC(min)
CKE ≤ 0.2V
M366S2953BTS (128M x 64, 1GB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating current
(One bank active)
Precharge standby current
in power-down mode
Precharge standby current
in non power-down mode
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
Symbol
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
Operating current
(Burst mode)
ICC4
Refresh current
ICC5
Self refresh current
ICC6
Notes : _{1. Measured with outputs open.}
2. Refresh period is 64ms.
Test Condition
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
tRC ≥ tRC(min)
CKE ≤ 0.2V
Version
7A
810
18
18
180
90
55
55
270
225
900
1,800
27
Version
7A
960
32
32
320
160
100
100
480
400
1,040
1,840
48
SDRAM
Unit
Note
mA
1
mA
mA
mA
mA
mA
mA
1
mA
2
mA
Unit
Note
mA
1
mA
mA
mA
mA
mA
mA
1
mA
2
mA
Rev. 1.1 February 2004