K4D64163HF Datasheet, PDF (13/16 Pages) Samsung semiconductor – 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM

K4D64163HF
C CHARACTERISTICS
64M DDR SDRAM
Parameter
Sym-
-33
bol _{Min Max}
K cycle time
CL=3 tCK
3.3
4.0
K high level width
tCH
0.45 0.55
K low level width
tCL
0.45 0.55
QS out access time from CK tDQSCK -0.6
0.6
utput access time from CK tAC
-0.6
0.6
ata strobe edge to Dout edge tDQSQ
-
0.4
ead preamble
tRPRE
0.9
1.1
ead postamble
tRPST
0.4
0.6
K to valid DQS-in
tDQSS
0.8
1.25
QS-In setup time
tWPRES
0
-
QS-in hold time
tWPREH 0.45
-
QS write postamble
tWPST
0.4
0.6
QS-In high level width
tDQSH
0.4
0.6
QS-In low level width
tDQSL
0.4
0.6
ddress and Control input setup tIS
0.9
-
ddress and Control input hold tIH
0.9
-
Q and DM setup time to DQS tDS
0.4
-
Q and DM hold time to DQS tDH
0.4
-
lock half period
tCLmin
tHP
or
-
tCHmin
ata output hold time from DQS tQH
tHP-0.4
-36
Min Max
3.6
6
0.45 0.55
0.45 0.55
-0.6
0.6
-0.6
0.6
-
0.4
0.9
1.1
0.4
0.6
0.85 1.15
0
-
0.35
-
0.4
0.6
0.4
0.6
0.4
0.6
0.9
-
0.9
-
0.4
-
0.4
-
tCLmin
or
-
tCHmin
tHP-0.4 -
-40
Min Max
4.0
7
0.45 0.55
0.45 0.55
-0.6
0.6
-0.6
0.6
-
0.4
0.9
1.1
0.4
0.6
0.85 1.15
0
-
0.35
-
0.4
0.6
0.4
0.6
0.4
0.6
0.9
-
0.9
-
0.4
-
0.4
-
tCLmin
or
-
tCHmin
tHP-0.4 -
-50
Min Max
5.0
10
0.45 0.55
0.45 0.55
-0.7
0.7
-0.7
0.7
-
0.45
0.9
1.1
0.4
0.6
0.8
1.2
0
-
0.3
-
0.4
0.6
0.4
0.6
0.4
0.6
1.0
-
1.0
-
0.45
-
0.45
-
tCLmin
or
-
tCHmin
tHP-
0.45
-
-60
Min Max
6.0
10
0.45 0.55
0.45 0.55
-0.75 0.75
-0.75 0.75
-
0.5
0.9
1.1
0.4
0.6
0.75 1.25
0
-
0.25
-
0.4
0.6
0.4
0.6
0.4
0.6
1.1
-
1.1
-
0.5
-
0.5
-
tCLmin
or
-
tCHmin
tHP-0.5 -
Unit Note
ns
tCK
tCK
ns
ns
ns 1
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns 1
ns 1
ote 1 :
The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst
ase
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
- 13 -
Rev. 1.1(Aug. 2002)