K4D553238F-JC Datasheet, PDF (13/17 Pages) Samsung semiconductor – 256Mbit GDDR SDRAM

K4D553238F-JC
AC CHARACTERISTICS
256M GDDR SDRAM
Parameter
Sym-
bol
CK cycle time
CL=3
CL=4
tCK
CK high level width
tCH
CK low level width
tCL
DQS out access time from CK tDQSCK
Output access time from CK tAC
Data strobe edge to Dout edge tDQSQ
Read preamble
tRPRE
Read postamble
tRPST
CK to valid DQS-in
tDQSS
DQS-In setup time
tWPRES
DQS-in hold time
tWPREH
DQS write postamble
tWPST
DQS-In high level width
tDQSH
DQS-In low level width
tDQSL
Address and Control input setup tIS
Address and Control input hold tIH
DQ and DM setup time to DQS tDS
DQ and DM hold time to DQS tDH
Clock half period
tHP
Data output hold time from DQS tQH
-2A
Min Max
-
10
2.86
0.45 0.55
0.45 0.55
-0.6 0.6
-0.6 0.6
-
0.35
0.9
1.1
0.4
0.6
0.85 1.15
0
-
0.35
-
0.4
0.6
0.4
0.6
0.4
0.6
0.9
-
0.9
-
0.35
-
0.35
-
tCLmin
or
-
tCHmin
tHP
-0.35
-
-33
Min Max
-
10
3.3
0.45 0.55
0.45 0.55
-0.6 0.6
-0.6 0.6
-
0.35
0.9
1.1
0.4
0.6
0.85 1.15
0
-
0.35
-
0.4
0.6
0.4
0.6
0.4
0.6
0.9
-
0.9
-
0.35
-
0.35
-
tCLmin
or
-
tCHmin
tHP
-0.35
-
-36
Min Max
-
10
3.6
0.45 0.55
0.45 0.55
-0.6 0.6
-0.6 0.6
-
0.40
0.9
1.1
0.4
0.6
0.85 1.15
0
-
0.35
-
0.4
0.6
0.4
0.6
0.4
0.6
0.9
-
0.9
-
0.40
-
0.40
-
tCLmin
or
-
tCHmin
tHP
-0.4
-
-40
Min Max
4.0
10
-
0.45 0.55
0.45 0.55
-0.6
0.6
-0.6
0.6
-
0.40
0.9
1.1
0.4
0.6
0.85 1.15
0
-
0.35
-
0.4
0.6
0.4
0.6
0.4
0.6
0.9
-
0.9
-
0.40
-
0.40
-
tCLmin
or
-
tCHmin
tHP
-0.4
-
-50
Min Max
5.0
10
-
0.45 0.55
0.45 0.55
-0.7
0.7
-0.7
0.7
-
0.45
0.9
1.1
0.4
0.6
0.8
1.2
0
-
0.3
-
0.4
0.6
0.4
0.6
0.4
0.6
1.0
-
1.0
-
0.45
-
0.45
-
tCLmin
or
-
tCHmin
tHP-
0.45
-
Unit Note
ns
ns
tCK
tCK
ns
ns
ns
1
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
1
ns
1
Simplified Timing @ BL=2, CL=4
0
1
CK, CK
tCH
tCL
tCK
2
3
4
5
CS
DQS
DQ
DM
COMMAND READA
tRPRE
tDQSCK
tRPST
tDQSQ
tAC
Qa1 Qa2
6
7
8
tIS
tIH
tDQSS
tWPREH
tDQSH
tDQSL
tWPRES
tDS tDH
Db0 Db1
WRITEB
- 13 -
Rev 1.0 (Mar. 2004)