K4D551638D Datasheet, PDF (13/18 Pages) Samsung semiconductor – 256Mbit GDDR SDRAM

K4D551638D-TC
256M GDDR SDRAM
AC CHARACTERISTICS
Parameter
CK cycle time
CL=3
CL=4
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
Clock half period
Data output hold time from DQS
Symbol
-2A
Min Max
tCK
-
10
2.86
tCH
0.45 0.55
tCL
0.45 0.55
tDQSCK -0.6 0.6
tAC
-0.6 0.6
tDQSQ
-
0.35
tRPRE
0.9
1.1
tRPST
0.4
0.6
tDQSS 0.85 1.15
tWPRES 0
-
tWPREH 0.35
-
tWPST
0.4
0.6
tDQSH
0.4
0.6
tDQSL
0.4
0.6
tIS
0.9
-
tIH
0.9
-
tDS
0.35
-
tDH
0.35
-
tCLmin
tHP
or
-
tCHmin
tQH
tHP-
0.35
-
-33
Min Max
-
10
3.3
0.45 0.55
0.45 0.55
-0.6 0.6
-0.6 0.6
-
0.35
0.9
1.1
0.4
0.6
0.85 1.15
0
-
0.35
-
0.4
0.6
0.4
0.6
0.4
0.6
0.9
-
0.9
-
0.35
-
0.35
-
tCLmin
or
-
tCHmin
tHP-
0.35
-
-36
Min Max
-
10
3.6
0.45 0.55
0.45 0.55
-0.6 0.6
-0.6 0.6
-
0.4
0.9
1.1
0.4
0.6
0.85 1.15
0
-
0.35
-
0.4
0.6
0.4
0.6
0.4
0.6
0.9
-
0.9
-
0.4
-
0.4
-
tCLmin
or
-
tCHmin
tHP-
0.4
-
-40
Min Max
-
10
4.0
0.45 0.55
0.45 0.55
-0.6 0.6
-0.6 0.6
-
0.4
0.9
1.1
0.4
0.6
0.85 1.15
0
-
0.35
-
0.4
0.6
0.4
0.6
0.4
0.6
0.9
-
0.9
-
0.4
-
0.4
-
tCLmin
or
-
tCHmin
tHP-
0.4
-
-45
Min Max
4.5
10
-
0.45 0.55
0.45 0.55
-0.7 0.7
-0.7 0.7
-
0.45
0.9
1.1
0.4
0.6
0.8
1.2
0
-
0.3
-
0.4
0.6
0.45 0.55
0.45 0.55
1.0
-
1.0
-
0.45
-
0.45
-
tCLmin
or
-
tCHmin
tHP-
0.45
-
Unit Note
ns
ns
tCK
tCK
ns
ns
ns 1
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns 1
ns 1
AC CHARACTERISTICS (I)
Parameter
Symbol
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay for Read
RAS to CAS delay for Write
tRC
tRFC
tRAS
tRCDRD
tRCDW
Row precharge time
tRP
Row active to Row active
tRRD
Last data in to Row precharge
@Normal Precharge
tWR
Last data in to Row precharge
@Auto Precharge
tWR_A
Last data in to Read command tCDLR
Col. address to Col. address
tCCD
Mode register set cycle time
tMRD
Auto precharge write recovery +
Precharge
tDAL
Exit self refresh to read command tXSR
Power down exit time
tPDEX
Refresh interval time
tREF
-2A
Min Max
15
-
17
-
10 100K
5
-
3
-
5
-
3
-
3
-
3
-
3
-
1
-
2
-
8
-
200
-
3tCK
+tIS
-
7.8
-
-33
Min Max
15
-
17
-
10 100K
5
-
3
-
5
-
3
-
3
-
3
-
3
-
1
-
2
-
8
-
200
-
3tCK
+tIS
-
7.8
-
-36
Min Max
15
-
17
-
10 100K
5
-
3
-
5
-
3
-
3
-
3
-
2
-
1
-
2
-
8
-
200
-
3tCK
+tIS
-
7.8
-
-40
Min Max
13
-
15
-
9
100K
4
-
2
-
4
-
3
-
3
-
3
-
2
-
1
-
2
-
7
-
200
-
3tCK
+tIS
-
7.8
-
-45
Min Max
12
-
14
-
8
100K
4
-
2
-
4
-
3
-
3
-
Unit Note
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK 1
3
-
tCK 1
2
-
tCK 1
1
-
tCK
2
-
tCK
7
-
tCK
200
-
tCK
3tCK
+tIS
-
ns
7.8
-
us
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
- 13 -
Rev 1.8 (Oct. 2003)