DS_M368L3223DTL Datasheet, PDF (11/12 Pages) Samsung semiconductor – 256MB DDR SDRAM MODULE

M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
Command Truth Table
COMMAND
Register
Register
Refresh
Extended MRS
Mode Register Set
Auto Refresh
Self
Refresh
Entry
Exit
Bank Active & Row Addr.
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
All Banks
Active Power Down
Entry
Exit
Precharge Power Down Mode
Entry
Exit
DM
No operation (NOP) : Not defined
CKEn-1
H
H
H
L
H
H
H
H
H
H
L
H
L
H
H
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
CKEn CS RAS CAS WE BA0,1 A10/AP
A11, A12
A9 ~ A0
X
L
L
L
L
OP CODE
X
L
L
L
L
OP CODE
H
L
L
L
H
X
L
L
H
H
H
H
X
H
X
X
X
X
L
L
H
H
V
Row Address
L
Column
X
L
H
L
H
V
Address
H
(A0~A9)
L
Column
X
L
H
L
L
V
Address
H
(A0~A9)
X
L
H
H
L
X
V
L
X
L
L
H
L
X
X
H
H
X
X
X
L
L
V
V
V
X
H
X
X
X
X
H
X
X
X
L
L
H
H
H
X
H
X
X
X
H
L
V
V
V
X
X
H
X
X
X
X
X
L
H
H
H
Note
1, 2
1, 2
3
3
3
3
4
4
4
4, 6
7
5
8
9
9
Note : 1. OP Code : Operand Code. A 0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank B is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A 10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.2 May. 2002