SA2030 Datasheet, PDF (9/12 Pages) Sames – PCM FRAME ALIGNER

SA2030
Route Subsystem Timing
(At V = 5V, T = 25°C)
DD
AMB
Characteristics
Sym Min
Typ Max Unit Test Conditions
Route Clock Period
T_RCL
400
488
600
ns Note 1, 2, 3
Route Clock Duty Cycle
D_RCL
25
50
75 % at 2,048MHz
Input Data Setup time
t_S
150
-
-
ns
Input Data Hold time
t
40
-
H
-
ns
Synch Pulse Width
t
-
488
-
ns In Frame Synch
SPW
Synch Pulse Delay
t_DOSP
-
-
200 ns In Frame Synch
Fault Pulse Width
t_FPW
-
1952
-
ns After Bad FAS
Fault Pulse Delay
t _DOFP
-
-
200 ns After Bad FAS
Synch Pulse Repeat Period T_SP
-
250
-
µs In Frame Synch
Fault Pulse Repeat Period
T_FP
-
250
-
µs Out of Frame
Synch
Note: 1. The CCITT recommends clock frequency of 2,048MHz ±50ppm.
2. Incorrect Slip operation may occur if the Route clock and System clock differ by
more than 1% (10000ppm).
3. A Synch Alarm will be issued if the Route Clock frequency is less than 75% of the
Station Clock frequency.
Route Subsystem Timing Diagram
sames
9/12