SA2030 Datasheet, PDF (7/12 Pages) Sames – PCM FRAME ALIGNER

SA2030
PIN DESCRIPTION
Pin No.
1
2
3
Name
DB1
DB2
SP
4
R/W
5
PE
6
RCL
7
SCL
8
BI
9
SCT
10
CE
11
SO
12
V_SS
13
P
14
B1
15
B2
16
B3
17
B4
18
B5
19
B6
20
B7
21
B8
22
IN
23
FP
24
V_DD
Function
Bidirectional Alarm Port
Bidirectional Alarm Port
Synchronisation Pulse output. Asserted during the bit interval immediately
prior to time-slot-zero of frames that contain FAS. Suppressed in the event
of frame-alignment loss.
Input for controlling direction of Alarm port data bus DB1 and DB2.
Internally pulled up to V_DD.
Alarm port enable. Asserting this pin enables data transfers to or from
DB1 and DB2. Internally pulled up to V .
DD
Route Clock Input. 2.048 MHz clock that defines PCM input data timing.
The route clock is usually extracted from the route data.
System Clock Input. 2.048 MHz clock that defines the timing of the
terminating equipment.
Buffer Inhibit Input. When true, the 1½ frame buffer is inhibited, and the
output frame timing is constrained to be within one-frame of the input
frame timing. When false, the full 1½ frame buffer is enabled, and
immunity to wander is maximised. Buffer Inhibit Mode of operation is
intended for delay compensation between switching stages in one exhange
system. Internally pulled up to V_DD.
Station Clock Trigger input. Low going pulse used by the host system to
define the required output frame timing. SCT should be asserted on
alternate frames, during the data-bit interval immediately prior to time-
slot-zero. SCT input is enabled by asserting CE.
Chip Enable input. When asserted the parallel outputs, B1 to B8 and P
are enabled. When CE = 1, parallel outputs are high impedance. CE must
also be asserted to enable the SCT input. Internally pulled-up to V_DD.
Serial PCM Data Output. PCM-30 format output of aligned and retimed
data. Data clocked out under control of the System Clock SCL.
Ground (0V) supply.
Parity Bit 3-state Ouput. Parity check for internal RAM. RAM data is saved
with Parity bit. Even Parity is used.
3-State PCM Parallel Output (PCM sign bit).
3-State PCM Parallel Output
3-State PCM Parallel Output
3-State PCM Parallel Output
3-State PCM Parallel Output
3-State PCM Parallel Output
3-State PCM Parallel Output
3-State PCM Parallel Output (LSB)
PCM data input. Data is derived from route data and is clocked into the
circuit on rising edges of RCL.
Fault Pulse Output. Fault pulses of 4 Route Clock cycles duration are
delivered whenever errors are detected in FAS, or on alternate frames in
the event of Frame Alignment loss.
Supply Voltage (+5V Nominal)
sames
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