SA2030 Datasheet, PDF (3/12 Pages) Sames – PCM FRAME ALIGNER

SA2030
FUNCTIONAL DESCRIPTION
PCM INPUT AND FRAME-ALIGNMENT
The SA2030 accepts route data on the IN input pin, on rising edges of the route clock RCL.
The circuit synchronises with the frame format of the incoming data by identification of
the Frame Alignment Signal (FAS) and the Service Word (SW) in time slot zero of the
PCM frame. The algorithm used for recovery and loss of frame synchronisation is in
accordance with CCITT recommendation G.737. After the circuit has gained
synchronisation with the incoming PCM-30 data stream, it outputs a synchronisation
pulse SP on alternate frames, during the bit interval prior to time-slot-zero of frames
containing the FAS word. The circuit will output a fault pulse on the FP output every time
errors are detected in the incoming FAS word. When the circuit is unable to synchronise
with the incoming data format, the SA2030 will generate a fault pulse every alternate
frame, and outgoing synchronisation pulses will be suppressed.
PCM OUTPUT
Data is clocked out on falling edges of the System Clock (SCL). PCM output is clocked
out serially on the SO output, and is made available in parallel on a tristate bus with parity
(B1-B8, P). The tristate outputs are enabled by asserting CE. The SA2030 must be
provided with a System Clock Trigger (SCT) pulse to define the required output frame
timing. The SCT pulse defines the bit interval immediately prior to the start of time-slot-
zero, on every alternate frame. Acceptance of SCT pulses is only enabled when CE is
asserted. The tristate parallel bus, with CE control, simplifies the use of the circuit in
multiplex and switching applications.
ELASTIC BUFFER
Incoming PCM data is saved in dual-ported RAM. The RAM has capacity for 1½ frames
of data. The SA2030 can thus accommodate any required frame delay between the
incoming data timing, and the required output frame timing. When the bounds of the
buffer are exceeded, whole frames are either dropped or repeated. The action of
dropping or repeating a received frame is called slip. Depending on the frame-delay, the
SA2030 can tolerate between ½ and 1½ frame of wander without requiring to alternately
repeat and drop frames. The design of the elastic buffer controller provides for correct
performance under severe clock-and-data-jitter conditions. The SA2030 exceeds the
requirements of CCITT recommendation G.823, and can be used to control jitter and
wander within digital networks. The 1½ frame buffer is enabled by setting BI = 0. If BI
= 1, the buffer length is limited to only one frame. The frame delay through the frame-
aligner is then constrained to be less than one frame. The buffer inhibit mode is useful
for delay compensation within a switching system, where drift and wander do not occur.
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