UM10601 Datasheet, PDF (302/313 Pages) NXP Semiconductors – LPC800 User manual

NXP Semiconductors
0x4000 C020) bit description . . . . . . . . . . . . .108
Table 105. Pin enable register 0 (PINENABLE0, address
0x4000 C1C0) bit description . . . . . . . . . . . . .108
Table 106. SCT pin description . . . . . . . . . . . . . . . . . . . . 112
Table 107. Register overview: State Configurable Timer
(base address 0x5000 4000) . . . . . . . . . . . . 115
Table 108. SCT configuration register (CONFIG, address
0x5000 4000) bit description . . . . . . . . . . . . 117
Table 109. SCT control register (CTRL, address 0x5000
4004) bit description . . . . . . . . . . . . . . . . . . . . 118
Table 110. SCT limit register (LIMIT, address 0x5000 4008)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .120
Table 111. SCT halt condition register (HALT, address
0x5004 400C) bit description . . . . . . . . . . . .120
Table 112. SCT stop condition register (STOP, address
0x5000 4010) bit description . . . . . . . . . . . .121
Table 113. SCT start condition register (START, address
0x5000 4014) bit description . . . . . . . . . . . .121
Table 114. SCT counter register (COUNT, address 0x5000
4040) bit description . . . . . . . . . . . . . . . . . . . .122
Table 115. SCT state register (STATE, address 0x5000
4044) bit description . . . . . . . . . . . . . . . . . . . .122
Table 116. SCT input register (INPUT, address 0x5000
4048) bit description . . . . . . . . . . . . . . . . . . . .123
Table 117. SCT match/capture registers mode register
(REGMODE, address 0x5000 404C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Table 118. SCT output register (OUTPUT, address 0x5000
4050) bit description . . . . . . . . . . . . . . . . . . . .124
Table 119. SCT bidirectional output control register
(OUTPUTDIRCTRL, address 0x5000 4054) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Table 120. SCT conflict resolution register (RES, address
0x5000 4058) bit description . . . . . . . . . . . .125
Table 121. SCT flag enable register (EVEN, address 0x5000
40F0) bit description . . . . . . . . . . . . . . . . . . . .126
Table 122. SCT event flag register (EVFLAG, address
0x5000 40F4) bit description . . . . . . . . . . . . .126
Table 123. SCT conflict enable register (CONEN, address
0x5000 40F8) bit description . . . . . . . . . . . . .126
Table 124. SCT conflict flag register (CONFLAG, address
0x5000 40FC) bit description . . . . . . . . . . . . .127
Table 125. SCT match registers 0 to 4 (MATCH[0:4],
address 0x5000 4100 (MATCH0) to 0x5000 4110
(MATCH4)) bit description (REGMODEn bit = 0) .
127
Table 126. SCT capture registers 0 to 4 (CAP[0:4], address
0x5000 4100 (CAP0) to 0x5000 4110 (CAP4)) bit
description (REGMODEn bit = 1) . . . . . . . . . .128
Table 127. SCT match reload registers 0 to 4
(MATCHREL[0:4], address 0x5000 4200
(MATCHREL0) to 0x5000 4210 (MATCHREL4) bit
description (REGMODEn bit = 0) . . . . . . . . . .128
Table 128. SCT capture control registers 0 to 4
(CAPCTRL[0:4], address 0x5000 4200
(CAPCTRL0) to 0x5000 4210 (CAPCTRL4)) bit
description (REGMODEn bit = 1) . . . . . . . . . .128
Table 129. SCT event state mask registers 0 to 5
UM10601 _Table
Table
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Table 132. SCT output clear register (OUT[0:3]_CLR,
address 0x5000 0504 (OUT0_CLR) to 0x5000
051C (OUT3_CLR)) bit description . . . . . . . . 131
Table 133. Event conditions . . . . . . . . . . . . . . . . . . . . . . 134
Table 134. Register overview: MRT (base address 0x4000
4000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 135. Time interval register (INTVAL[0:3], address
0x4000 4000 (INTVAL0) to 0x4000 4030
(INTVAL3)) bit description . . . . . . . . . . . . . . . 142
Table 136. Timer register (TIMER[0:3], address 0x4000 4004
(TIMER0) to 0x4000 4034 (TIMER3)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 137. Control register (CTRL[0:3], address 0x4000
4008 (CTRL0) to 0x4000 4038 (CTRL3)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 138. Status register (STAT[0:3], address 0x4000 400C
(STAT0) to 0x4000 403C (STAT3)) bit description
144
Table 139. Idle channel register (IDLE_CH, address 0x4000
40F4) bit description . . . . . . . . . . . . . . . . . . . 144
Table 140. Global interrupt flag register (IRQ_FLAG, address
0x4000 40F8) bit description . . . . . . . . . . . . . 145
Table 141. Register overview: Watchdog timer (base
address 0x4000 4000) . . . . . . . . . . . . . . . . . . 150
Table 142. Watchdog mode register (MOD - 0x4000 4000)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 143. Watchdog operating modes selection . . . . . . 152
Table 144. Watchdog Timer Constant register (TC - 0x4000
4004) bit description. . . . . . . . . . . . . . . . . . . . 152
Table 145. Watchdog Feed register (FEED - 0x4000 4008)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 146. Watchdog Timer Value register (TV - 0x4000
400C) bit description . . . . . . . . . . . . . . . . . . . 153
Table 147. Watchdog Timer Warning Interrupt register
(WARNINT - 0x4000 4014) bit description. . . 153
Table 148. Watchdog Timer Window register (WINDOW -
0x4000 4018) bit description . . . . . . . . . . . . . 154
Table 149. Analog comparator pin description . . . . . . . . 156
Table 150. Register overview: Analog comparator (base
address 0x4002 4000) . . . . . . . . . . . . . . . . . . 158
Table 151. Comparator control register (CTRL, address
0x4002 4000) bit description . . . . . . . . . . . . . 158
Table 152. Voltage ladder register (LAD, address 0x4002
4004) bit description. . . . . . . . . . . . . . . . . . . . 160
Table 153. Register overview: WKT (base address 0x4000
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 154. Control register (CTRL, address 0x4000 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 155. Counter register (COUNT, address 0x4000 800C)
UM10601
Preliminary user manual
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Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
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