UM10601 Datasheet, PDF (167/313 Pages) NXP Semiconductors – LPC800 User manual

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• Enable the USART interrupt in the NVIC.
• The USART wakes up the part from Deep-sleep or Power-down mode on all events
that cause an interrupt and also are enabled in the INTENSET register. Typical
wake-up events are:
– A received start bit has been detected.
– An address bit has been sent.
– The RXDATA buffer has received one byte and is full.
– Data are ready to be transmitted in the TXDATA buffer and a serial clock from the
master has been received.
– A change in the state of the CTS pin if the CTS function is connected. <tbd>
– Remark: By enabling or disabling the interrupt in the INTENSET register
(Table 161), you can customize when the wake-up occurs in the USART
receive/transmit protocol.
15.4 Pin description
The USART receive, transmit, and control signals are movable functions and are
assigned to external pins through the switch matrix.
See Section 9.3.1 “Connect an internal signal to a package pin” to assign the USART
functions to pins on the LPC800 package.
Table 156. USART pin description
Function Direction Pin Description
SWM register
U0_TXD O
any Transmitter output for USART0. Serial transmit data.
PINASSIGN0
U0_RXD I
any Receiver input for USART0. Serial receive data.
PINASSIGN0
U0_RTS O
any Request To Send output for USART0. Active low signal for PINASSIGN0
supports inter-processor communication through the use of
hardware flow control. This feature is active when the
USART RTS signal is configured to appear on a device pin.
U0_CTS I
any Clear To Send input for USART0. Active low signal indicates PINASSIGN0
if the external device that is in communication with the
USART is ready to accept data. This feature is active when
enabled by the CTSEn bit in CFG register and when
configured to appear on a device pin. When deasserted
(high) by the external device, the USART will complete
transmitting any character already in progress, then stop
until CTS is again asserted (low).
Reference
Table 96
Table 96
Table 96
Table 96
UM10601
Preliminary user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
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