UM10601 Datasheet, PDF (116/313 Pages) NXP Semiconductors – LPC800 User manual

UM10601 NXP Semiconductors
Table 107. Register overview:
Name
Access
MATCH0 to MATCH4 R/W
MATCH_L0 to
R/W
MATCH_L4
S_00Ao00ta_{xxxxfdft1111sde1100er0000}Cet _{sottoosnfiDS4S4R}g_;;CCue_ElRsroTTGa_EcwMb_mmrGilcOpaae_MotttDuccTi_OohhnEim_{Dnt4vve0_}e_aarLr_llt1uuo(_6ee=b_R-a_rrb0^C_eeEs_itggG^h_;e_iiRss^a_Ma_tt^p_Eeed_OrrG^td^e_Door_M^re_{Eff O}s_mm¹₄s⁰_Daa=^:0_tt0cc0x^L_{_hh}5_L^P0_cct^C_hh0_oaa0⁸_nn⁰4_nn⁰0_ee0_ll^S_ss0^Dt)₀₀^aR…^t_tt^Ae_oo^Fc^TCon^D_R0-^ot^Ri_xen^nA₀^Du_s^fF₀^Reⁱ_e^Tg₀d^A_t0^DuF_v^TRr_0a^AaD_l0u^FbR₀^T_e^ADl₀^eDFRTRAT_RTTAFDaaⁱ_e^TFRm_bbTf^AD_ellee^eDFR_r^TrRD_e^A_11An^RFD(₂₂^STFAR_{c44TFeADCTDFRTTRDA)ARDFTFDARTRFADTADFRTFRDATADRF}
MATCH_H0 to
MATCH_H4
R/W 0x102 to SCT match value register of match channels 0 to -
0x112 4; high counter 16-bit; REGMOD0_H to
REGMODE4_H = 0
Table 124
CAP0 to CAP4
0x100 to SCT capture register of capture channel 0 to 4; 0x0000 0000 Table 126
0x110 REGMOD0 to REGMODE4 = 1
CAP_L0 to CAP_L4
0x100 to SCT capture register of capture channel 0 to 4; -
0x110 low counter 16-bit; REGMOD0_L to
REGMODE4_L = 1
Table 126
CAP_H0 to CAP_H4
0x102 to SCT capture register of capture channel 0 to 4; -
0x13E high counter 16-bit; REGMOD0_H to
REGMODE4_H = 1
Table 126
MATCHREL0 to
MATCHREL4
R/W 0x200 to SCT match reload value register 0 to 4
0x210 REGMOD0 = 0 to REGMODE4 = 0
0x0000 0000 Table 127
MATCHREL_L0 to R/W 0x200 to SCT match reload value register 0 to 4; low
-
MATCHREL_L4
0x210 counter 16-bit; REGMOD0_L = 0 to
REGMODE4_L = 0
Table 127
MATCHREL_H0 to R/W 0x202 to SCT match reload value register 0 to 4; high
-
MATCHREL_H4
0x212 counter 16-bit; REGMOD0_H = 0 to
REGMODE4_H = 0
Table 127
CAPCTRL0 to
CAPCTRL4
0x200 to SCT capture control register 0 to 4; REGMOD0 = 0x0000 0000 Table 128
0x210 1 to REGMODE4 = 1
CAPCTRL_L0 to
CAPCTRL_L4
0x200 to SCT capture control register 0 to 4; low counter -
0x210 16-bit; REGMOD0_L = 1 to REGMODE4_L = 1
Table 128
CAPCTRL_H0 to
CAPCTRL_H4
0x202 to SCT capture control register 0 to 4; high counter -
0x212 16-bit; REGMOD0 = 1 to REGMODE4 = 1
Table 128
EV0_STATE
R/W 0x300 SCT event 0 state register
0x0000 0000 Table 129
EV0_CTRL
R/W 0x304 SCT event 0 control register
0x0000 0000 Table 130
EV1_STATE
R/W 0x308 SCT event 1 state register
0x0000 0000 Table 129
EV1_CTRL
R/W 0x30C SCT event 1 control register
0x0000 0000 Table 130
EV2_STATE
R/W 0x310 SCT event 2 state register
0x0000 0000 Table 129
EV2_CTRL
R/W 0x314 SCT event 2 control register
0x0000 0000 Table 130
EV3_STATE
R/W 0x318 SCT event 3 state register
0x0000 0000 Table 129
EV3_CTRL
R/W 0x31C SCT event 3 control register
0x0000 0000 Table 130
EV4_STATE
R/W 0x320 SCT event 4 state register
0x0000 0000 Table 129
EV4_CTRL
R/W 0x324 SCT event 4 control register
0x0000 0000 Table 130
EV5_STATE
R/W 0x328 SCT event 5 state register
0x0000 0000 Table 129
EV5_CTRL
R/W 0x32C SCT event 5 control register
0x0000 0000 Table 130
OUT0_SET
R/W 0x500 SCT output 0 set register
0x0000 0000 Table 131
OUT0_CLR
R/W 0x504 SCT output 0 clear register
0x0000 0000 Table 132
OUT1_SET
R/W 0x508 SCT output 1 set register
0x0000 0000 Table 131
UM10601
Preliminary user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
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