UM10601 Datasheet, PDF (211/313 Pages) NXP Semiconductors – LPC800 User manual

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(an unusual case), the SPI should be disabled and re-enabled with the new configuration.
Table 189. SPI Configuration register (CFG, addresses 0x4005 8000 (SPI0) , 0x4005 C000 (SPI1)) bit
description
Bit Symbol Value Description
0
Enable
SPI enable.
Reset
value
0
0
Disabled. The SPI is disabled and the internal state machine and counters are reset.
1
Enabled. The SPI is enabled for operation.
1
-
Reserved. Read value is undefined, only zero should be written.
NA
2
Master
Master mode select.
0
0
Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are
inputs, MISO is an output.
1
Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals
are outputs, MISO is an input.
3
LSBF
LSB First mode enable.
0
0
Standard. Data is transmitted and received in standard MSB first order.
1
Reverse. Data is transmitted and received in reverse order (LSB first).
4
CPHA
Clock Phase select.
0
0
Change. The SPI captures serial data on the first clock transition of the frame (when the
clock changes away from the rest state). Data is changed on the following edge.
1
Capture. The SPI changes serial data on the first clock transition of the frame (when the
clock changes away from the rest state). Data is captured on the following edge.
5
CPOL
Clock Polarity select.
0
0
Low. The rest state of the clock (between frames) is low.
1
High. The rest state of the clock (between frames) is high.
6
-
Reserved. Read value is undefined, only zero should be written.
NA
7
LOOP
Loopback mode enable. Loopback mode applies only to Master mode, and connects
0
transmit and receive data connected together to allow simple software testing.
0
Disabled.
1
Enabled.
8
SPOL
SSEL Polarity select.
0
0
Low. The SSEL pin is active low. The value in the SSEL fields of the RXDAT, TXDATCTL,
and TXCTL registers related to SSEL is not inverted relative to the pins.
1
High. The SSEL pin is active high. The value in the SSEL fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL is inverted relative to the pins.
31:9 -
Reserved. Read value is undefined, only zero should be written.
NA
UM10601
Preliminary user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
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