BU9832GUL-W Datasheet, PDF (9/14 Pages) Rohm – Silicon Monolithic Integrated Circuit

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◇TIMING CHART
1.WREN （WRITE ENABLE）
CSB
SCK
01 2 3 4 5 6 7
SI
00 0 0
0110
SO ^Hi-Z
Fig.7 WRITE ENABLE CYCLE TIMING
CSB
SCK
01 2 3 4 5 6 7
SI
00 0 0
0 1 00
SO
Hi-Z
Fig.8 WRITE DISABLE CYCLE TIMING
2.WRDI (WRITE DISABLE)
The device has both of the enable and disable mode. After “Write Enable” is executed, the device
becomes in the enable mode. After “Write Disable” is executed, the device becomes in the disable
mode. After CS goes low, each of Op.code is recognized at the rising edge of 7th clock. Each of
instructions is effective inputting seven or more SCK clocks.
This “Write Enable” instruction must be proceeded before the any write commands.
The device ignores inputting the any write commands in the disable mode.
Once the any write commands is executed in the enable mode, the device becomes the disable
mode.
After the power become on, the device is in the disable mode.
REV. B