BU9832GUL-W Datasheet, PDF (7/14 Pages) Rohm – Silicon Monolithic Integrated Circuit

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◇Functional Description
○Status Register
The device has status register.
Status register consists of 8bits and is shown following parameters.
3bits(WPEN, BP0 and BP1) are set by “Write Status Register” commands, which are non-volatile.
Specification of endurance and data retention are as well as memory array.
WEN bit is set by “Write enable” and “Write Disable” commands. After power become on, the device is disable
mode. R/B bit is a read-only and status bit. The device is clocked out value of the
status register by “Read Status Register” command input.
Bit7
Bit6
WPEN
0
Bit
WPEN
BP0/BP1
WEN
R/B
Bit5
Bit4
Bit3
Bit2
0
0
BP1
BP0
Definition
WP pin ENABLE Bit
WPEN=0 ： no use WPEN=1 Protect
Block write protection for memory array
（EEPROM）
Write enable/disable state bit
WEN=0 ： write disable
WEN=1 ： write enable
READY／BUSY status bit
R/B=0 ： READY
R/B=1 ： BUSY
Table1. Status Register
Bit1
Bit0
WEN
R/B
×:Don't care
BP1
BP0
Block Write Protection
0
0
0
1
1
0
1
1
None
300h-3FFh
200h-3FFh
000h-3FFh
Table2. Block Write Protection
○WP pin
The device inhibits to write the data into status register during WP is low. WPEN bit in status register needs
to be high to enable WP pin function.
○HOLD pin
HOLD pin is able to suspend data transmission for a time (Hold state). HOLD pin is normally high for
transmission of the data. SCK and SI input are “Don’t Care” and SO output state is
Hi-Z for hold state.
After HOLD pin is brought high to release hold state during SCK is low, the device resumes to transfer the data.
For example, in case the device is hold state after A5 (the address data) input in read command, to resume the
data transmission enable starting A4 (the address data) input
after hold state is release. When CS is brought high with hold state, the device is reset and cannot resume the
data transmission.
REV. B