BU9888FV-W Datasheet, PDF (7/17 Pages) Rohm – High Reliability Serial EEPROMs

BU9888FV-W
Technical Note
3. Write enable (WEN)
CS
SK
1 2 3 4 5 6 7 8 9 10 11
DI
10011
DO _High-Z
Fig.27
Write enable (WEN) cycle
○At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is
necessary to execute the write enable command. And, once this command is executed, it is valid unitl the write disable
command is executed or the power is turned off. However, the read command is valid irrespective of write enable /
diable command. Input to SK after 8 clocks of this command is available by either “H” or “L”, but be sure to input it.
4. Write disable (WDS) cycle
CS
SK
1 2 3 4 5 6 7 8 9 10 11
DI
10000
DO _High-Z
Fig.28 Write disable (WDS) cycle
○When the write enable command is executed after power on, write enable status gets in. When the write disable
command is executed then, the IC gets in write disable status as same as at power on, and then the write command is
canceled thereafter in software manner. However, the read command is executable. In write enable status, even when
the write command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the
write disable command after completion of write. Input to SK after 8 clocks of this command is available by either “H” or
“L”, but be sure to input it.
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2011.01 - Rev.A