BU9888FV-W Datasheet, PDF (6/17 Pages) Rohm – High Reliability Serial EEPROMs

BU9888FV-W
Technical Note
●Timing chart
1. Read cycle (READ)
CS
～～
～～
～～
（※1）
～～
SK
12
4
12
～～
27 28
～～
～～
DI
1 1 0 A7 A6 _{～ ～} A1 A0
～～
DO _High-Z
～～
～～
（※2）
～～
0 D15 D1_～ 4_～
D1 D0 D15 D1_{～ ～}4
Fig.25 Read cycle
(※2）Next address data(Auto increment function)
(※1) Start bit
When data “1” is input for the first time after the rise of CS, this is recognized as a start bit. And when “1” is input after plural “0” are input, it is recognized
as a start bit, and the following operation is started. This is common to all the commands to described hereafter.
○When the read command is recognized, input address data (16bit) is output to serial. And at that moment, at taking A0,
in sync with the rise of SK, “0” (dummy bit) is output. And, the following data is output in sync with the rise of SK. This IC
has an address auto increment function valid only at read command. This is the function where after the above read
execution, by continuously inputting SK clock, the above address data is read sequentially. And, during the auto
increment, keep CS at “H”.
2. Write cycle (WRITE)
CS
SK
12
4
DI
1 0 1 A7 A6
DO _High-Z
～～
～～
tCS
～～
11 12
～～
～ ～ ^{A1 A0 D15 D14}
～～
27
～～
～ ～ ^{D1 D0}
～～
～～
Fig.26 Write cycle
～～
STATUS
～～
～～
～～
tSV
BUSY
～～
tE/W
READY
○In this command, input 16bit data (D15～D0) are written to designated addresses (A7~A0). The actual write starts by the
fall of CS of D0 taken SK clock. When STATUS is not detected, (CS=”L” fixed) Max. 2ms in conformity with tE/W, and
when STATUS is detected (CS=”H”), all commands are not accepted for areas where “L” ( BUSY ) is output from D0,
therefore, do not input any command.
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2011.01 - Rev.A