BU97540KV-M Datasheet, PDF (61/70 Pages) Rohm – Multi-function Segment Drivers

BU97540KV-M
Voltage Detection Type Reset Circuit (VDET)
The Voltage Detection Type Reset Circuit generates an output signal that resets the system when power is applied for
the first time and when the power supply voltage drops (that is, for example, the power supply voltage is less than or equal to
the power down detection voltage (VDET = 1.8V typ.). To ensure that this reset function works properly, it is recommended that
a capacitor be connected to the power supply line so that both the power supply voltage (VDD) rise time when power is first
applied and the power supply voltage (VDD) fall time when the voltage drops are at least 1ms.
VDD
t1
t2
VDD min
VDD min
t3
VDD = 1.0V
Figure 39. VDET Detection Timing
Power supply voltage VDD fall time: t1 > 1ms
Power supply voltage VDD rise time: t2 > 1ms
Internal reset power supply retain time: t3 > 1ms
Reset Condition
When BU97540KV-M is initialized, the internal status after power supply has been reset as the following table.
Control Data Reset Condition
Instruction
At Reset Condition
Key Scan Mode
[KM0,KM1,KM2]=[1,1,1]:Keyscan no use
S1/P1/G1 to S9/P9/G9 Pin
[P0,P1,P2,P3]=[0,0,0,0]:all segment output
Inversion Mode
FL=0:Line Inversion
LCD Bias
DR=0:1/3 bias
LCD Duty
[DT0,DT1]=[0,1]:1/4 duty
DISPLAY Frequency
[FC0,FC1,FC2,FC3]=[0,0,0,0]:fosc/12288
Display Clock Mode
OC=0:Internal oscillator
LCD Display
SC=1:OFF
Power Mode
[BU0, BU1, BU2]=[1,1,1]:Power saving mode
PWM/GPO Output
PGx=0:PWM output(x=1～9)
PWM Frequency
[PF0,PF1,PF2,PF3]=[0,0,0,0]: fosc /4096
PWM Duty
[Wn0～Wn8]=[0,0,0,0,0,0,0,0,0]:0/256)xTp
(n=1～9,Tp=1/fp)
Display Contrast Setting [CT0,CT1,CT2,CT3]=[0,0,0,0]:VLCD Level is 1.00*VDD
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29.Jun.2015 Rev.002