BU97540KV-M Datasheet, PDF (6/70 Pages) Rohm – Multi-function Segment Drivers

BU97540KV-M
MPU Interface Characteristics (Ta=-40 to +85°C, VDD = 2.7V to 6.0V, VSS=0V)
Parameter
Symbol
Pin
Conditions
Min
Limit
Typ
Max
Unit
Data Setup Time
tds SCL, SDI
120
-
-
ns
Data Hold Time
tdh SCL, SDI
120
-
-
ns
SCE Wait Time
tcp SCE, SCL
120
-
-
ns
SCE Setup Time
tcs SCE, SCL
120
-
-
ns
SCE Hold Time
tch SCE, SCL
120
-
-
ns
Clock Cycle Time
tccyc SCL
320
-
-
ns
High-level Clock Pulse
Width
tchw SCL
120
-
-
ns
Low-level Clock Pulse
Width (Write)
tclww SCL
120
-
-
ns
Low-level Clock Pulse
Width (Read)
tclwr SCL
RPU=4.7KΩ
CL=10pf^(Note5)
1.6
-
-
us
Rise Time
tr SCE, SCL, SDI
-
160
-
ns
Fall Time
tf
SCE, SCL, SDI
-
160
-
ns
SDO Output Delay
Time
tdc SDO
RPU=4.7KΩ
CL=10pf^(Note5)
-
-
1.5
µs
SDO Rise Time
Tdr SDO
RPU=4.7KΩ
CL=10pf^(Note5)
-
-
1.5
µs
(Note5) Since SDO is an open-drain output, ”tdc” and “tdr” depend on the resistance of the pull-up resistor RPU and the load capacitance SCL.
RPU: 1kΩ≤RPU≤10kΩ is recommended.
CL: A parasitic capacitance to VSS in an application circuit. Any component is not necessary to be attached.
Power supply for I/O level
SDO
RPU
Host
CL
1. When SCL is stopped at the low level
SCE
SCL
SDI
VIH1, VIH2
VIL1
tr
tccyc
tchw
tclww
tf
VIH1, VIH2
VIL1
VIH1, VIH2
tcs
tclwr
VIL1
tch
SDO
tds
tdh
VOL5
tdc
tdr
2. When SCL is stopped at the high level
SCE
VIH1, VIH2
SCL
VIH1,VIH2
VIL1
tccyc
tclww
tchw
tf
tr
SDI
VIH1,VIH2
VIL1
tds
tdh
SDO
tclwr
tcp
tdc
Figure 5.Serial Interface Timing
VOL5
VIL1
tch
tdr
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TSZ02201-0P4P0D300970-1-2
29.Jun.2015 Rev.002