BU26154MUV Datasheet, PDF (45/89 Pages) Rohm – High PSRR is attained by built-in regulator

BU26154MUV
Datasheet
Register details explanation
Note: “-” indicates a reserved bit. They return “0” for read. Write “0” to the bit every time. If “1” is written to this bit, the
operations cannot be guaranteed.
Don’t write data to empty INDEX or register bit to guarantee normal operation.
A function with (*)bit doesn’t need internal clock to change state.
Sampling Rate Setting Register
MAPCON
INDEX
b07
b06
b05
b04
b03
b02
b01
b00
R
W
(Initial)
0x0
0x00 0x01
-
-
-
-
SR
-
-
-
-
0
0
0
0
This register sets the sampling rate of the recording/playback. Please perform the change of this register level in
RECPLAY=0x0) at a recording/playback stop.
SR [3:0]
Setting
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
Explanation
8kHz
11.025 kHz
12kHz
16kHz
22.05 kHz
24kHz
32kHz
44.1 kHz
48kHz
Clock Enable Register
MAPCON
INDEX
b07
b06
b05
b04
b03
b02
b01
b00
R
W
(Initial)
0x0
0x0c 0x0d TCLKEN
-
-
-
-
PLLOE PLLEN MCLKEN
0
-
-
-
-
0
0
0
This register is a register to control the operation of the clock.
MCLKEN
This bit sets permission / stop of the input of the MCLKI terminal. The input logic of the MCLKI terminal becomes invalid at
the time of the stop and clock is not transmitted to the LSI inside.
Setting
Explanation
0
MCLKI terminal input stop
A clock stops at the input first grade of the terminal
1
MCLKI terminal input permission
PLLEN
This bit sets movement / stop of PLL.
Setting
Explanation
0
PLL stop
1
PLL movement
After setting the PLL Setting register, please set PLLEN bit to "1".
PLLOE
This bit is to set the status of PLL output. Set this bit to “1” after PLL operation has stabilized. Also, this bit must be set to
“1” if PLL is not used, otherwise internal clock cannot be provided.
Setting
Explanation
0
The PLL output is put under ban
1
PLL output permission
TCLKEN
This bit sets the clock for the touch panel interface circuit.
TCLKEN
Explanation
0
Disable clock for the touch panel interface.
1
Enable clock for the touch panel interface.
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TSZ02201-0V1V0R501570-1-2
23.Jun.2014 Rev.001