BU26154MUV Datasheet, PDF (35/89 Pages) Rohm – High PSRR is attained by built-in regulator

BU26154MUV
Datasheet
Operating Mode
Normal operating mode
It becomes Normal operating mode by setting Touch ADC Control registerTCHA2=0x1. Next AD conversion starts by
reading register value of ADCR1 register (8Bit mode) or ADCR2 register (12Bit mode), at Normal operating mode.
TCLKEN Bit
Internal Clk
I2C Operation
SCL
SDA
Internal ADC Start Sync
ADC Status
IDLE
ADCR1Register
ADCR2 Register
Write Data reception
INDEX=0x61,TCHEN="1"
D2 D1 D0 ACK
Data Hold
Slave address receptio Read Data reception
INDEX=0x64
1 0 R ACK D7 D6 D5
AD Conversion1_1 AD Conversion1_2
Data Valid1_1
IDLE
Data Valid1_2
Data Hold
AD Conversion2_1 AD Conversion2_2
Data Valid2_1
IDLE
Data Valid2_2
Tw_ADC1
Tw_ADC2
12Bit Normal Mode I2C Timing
Tw_ADC1
Tw_ADC2
TCLKEN Bit
Internal Clk
I2C Operation
SCL
SDA
Internal ADC Start Sync
ADC Status
IDLE
ADCR1Register
ADCR2 Register
Write Data reception
INDEX=0x61,TCHEN="1"
D2 D1 D0 ACK
Data Hold
AD Conversion1
IDLE
Data Valid1
Slave address receptio Read Data reception
INDEX=0x62
1 0 R ACK D7 D6 D5
Data Hold
AD Conversion2
IDLE
Data Valid2
Tw_ADC1
8Bit Normal Mode I2C Timing
Tw_ADC1
AD conversion starts by rising edge of CSB at using SPI. 12Bit timing mode chart is listed below. 8Bit mode start timing is
similar it.
TCLKEN Bit
Internal Clk
SPI Operation
SCLK
CSB
Internal ADC Start Sync
ADC Status
IDLE
ADCR1Register
ADCR2 Register
Write Data
INDEX=0x61,TCHEN="1"
Data Hold
Read Data
INDEX = 0x64
AD Conversion1_1 AD Conversion1_2
Data Valid1_1
IDLE
Data Valid1_2
Tw_ADC1
Tw_ADC2
8Bit Normal Mode SPI Timing
Data Hold
AD Conversion2_1 AD Conversion2_2
Data Valid2_1
Idle
Data Valid2_2
Tw_ADC1
Tw_ADC2
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TSZ02201-0V1V0R501570-1-2
23.Jun.2014 Rev.001