BU9832GUL-W_12 Datasheet, PDF (4/30 Pages) Rohm – WLCSP EEPROM

BU9832GUL-W (8Kbit)
Datasheet
●Sync data input / output timing
CS
SCK
tCS
tSCKS
tCSS
SI
SO
tSCKWL tSCKWH
tDIS tDIH
High-Z
tRC
tFC
"H"
CS
"L"
SCK
tHFS tHFH
SI
n+1
SO
Dn+1
tHOZ
Dn
HOLD
tHRS tHRH
High-Z
tDIS
n
tHPD
Dn
n-1
Dn-1
Figure 1. Input timing
SI is taken into IC inside in sync with data rise edge of
SCK. IInput address and data from the most
significant bit MSB.
Figure 3. HOLD timing
CS
SCK
SI
SO
tPD
tOH
tCS
tCSH ^tSCKH
tRO,tFO tOZ
High-Z
Figure 2. Input / Output timing
SO is output in sync with data fall edge of SCK. Data is
output from the most significant bit MSB.
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
4/26
TSZ02201-0R2R0G100410-1-2
30.AUG.2012 Rev.001