BU9832GUL-W_12 Datasheet, PDF (19/30 Pages) Rohm – WLCSP EEPROM

BU9832GUL-W (8Kbit)
Datasheet
●Method to cancel each command
○READ
・Method to cancel : cancel by CS = “H”
Ope code
8 bits
Address
8 bits
Data
8 bits
Cancel available in all areas of read mode
○RDSR
・Method to cancel : cancel by CS = “H”
Figure 42. READ cancel valid timing
Ope code
Data
8 bits
8 bits
Cancel available in all
areas of rdsr mode
○WRITE, PAGE WRITE
a: Ope code, address input area.
Cancellation is available by CS =”H”
b: Data input area (D7 to D1 input area)
Cancellation is available by CS =”H”
c: Data input area (D0 area)
When CS is started, write starts.
After CS rise, cancellation cannot be made by any means.
d: tE/W area.
Cancellation is available by CS = “H”. However, when write
starts ( CS is started) in the area c, cancellation cannot be
made by any means. And by inputting on SCK clock,
cancellation cannot be made. In page write mode, there is
write enable area at every 8 clocks.
Figure 43. RDSR cancel valid timing
Ope code
8bits
a
Address
8bits
Data(n)
8bits
b
tE/W
d
c
Figure 44. WRITE cancel valid timing
SCK
SI ^{D7 D6 D5 D4 D3 D2 D1 D0}
b
c
Note 1)
Note 2)
If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again.
If CS is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore,
it is necessary to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher.
○WRSR
a: From ope code to 15 rise.
Cancel by CS =”H”.
b: From 15 clock rise to 16 clock rise (write enable area).
When CS is started, write starts.
After CS rise, cancellation cannot be made by any means.
c: After 16 clock rise.
Cancel by CS =”H”. However, when write starts ( CS is started)
in the area b, cancellation cannot be made by any means.
And, by inputting on SCK clock, cancellation cannot be made.
SCK
14 15 16 17
SI
D1 D0
a
b
c
Ope code
Address
tE/W
8 bits
8 bits
a
c
b
Figure 45. WRSR cancel valid timing
Note 1)
Note 2)
If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again
If CS is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is
necessary to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher.
○WREN/WRDI
a: From ope code to clock rise, cancel by CS = “H”.
b: Cancellation is not available when CS is started after 7 clock.
SCK
789
a
b
Ope code
8 bits
a
b
Figure 46. WREN/WRDI cancel valid timing
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TSZ22111・15・001
19/26
TSZ02201-0R2R0G100410-1-2
30.AUG.2012 Rev.001