BU94605AKV Datasheet, PDF (26/84 Pages) Rohm – AAC/WMA/MP3 +SD Memory Card +CD-ROM+MP3 Record

BU94605AKV BU94607AKV BU94702AKV BU94705AKV
Datasheet
8.5 I²C Bus line timing
Table 10. Timing
SDA and SCL bus-line characteristic (Unless specified, Ta=25℃, VDD1=3.3V)
Rating
Item
Symbol
min
typ
max
SDA, SCL H input voltage
VIH
VDD1*0.7
-
VDD1
SDA, SCL L input voltage
VIL
DVSS
-
VDD1*0.3
SDA H output voltage
VOH
VDD1-0.4
-
VDD1
SDA L output voltage
VOL
0
-
0.4
SCL clock frequency
fSCL
0
-
400
Bus-free-time between "Stop"
tBUF
1.3
-
-
condition and "Start" condition
Hold time for "Start" condition
After this, the first clock pulse is ^tHD;DAT
0.6
-
-
generated.
LOW status hold-time of
SCL clock
tLOW
1.3
-
-
HIGH status hold-time of
SCL clock
tHIGH
0.6
-
-
Data-hold-time
tHD;DAT
0*
-
-
Date-setup-time
tSU;DAT
100
-
-
Rising time of SDA and
SCL signal
tR
20+0.1*Cb
-
300
Fall time of SDA and SCL signal
tF
20+0.1*Cb
-
300
Setup time of "Stop" condition
tSU;STO
0.6
-
-
Capacitive load of each bus-line
Cb
－
-
400
Unit
V
V
V
V
kHz
us
us
us
us
us
ns
ns
ns
us
pF
Remarks
The above-mentioned numerical values are all the values corresponding to V_{IH min} and V_{IL max} level.
*To exceed an undefined area on falling edged of SCL, transmission device should internally offer the hold-time of
300ns or more for SDA signal (V_{IH min} of SCL signal).
Because the "Repeated Start" condition to send "Start" condition without sending "Stop" condition doesn't correspond,
after sending "Start" condition, always send "Stop" condition.
Neither terminal SCL nor terminal SDA correspond to 5V tolerant.
SDA
t_BUF
t_F
t_LOW
t_R
SCL
t_HD;STA
t_HD;DAT
P
S
t_HIGH
t_SU;DAT
Figure 28. I²C Bus line timing
t_SU;STO
P
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2012.12.10 Rev.002