BU9873 Datasheet, PDF (20/40 Pages) Rohm – I2C BUS Serial Interface RTC with High-precision Oscillation Adjustment

BU9873
Datasheet
5-2. Alarm Interrupt Output
Alarm interrupt output is from INTRB pin and the outputting is “L”. In addition, by monitoring the value of AAFG, BAFG bits
(internal address Fh), the state of alarm can be checked.
Alarm_A (Alarm_B) Flag Bit
AAFG, BAFG
Description
0
Unmatched alarm register with clock counter
1
Matched alarm register with clock counter
Default
The flag bit turns to “1” and INTRB is “L” when matched time is sensed for each alarm.
The AAFG, BAFG bit may be set only to “0”. Setting this bit to“0” sets the INTRB to OFF status (“H”). When this bit is set to“1”
nothing happens. When the AALE, BALE bit is set to“0”, alarm operation is disabled and “0“is read from the AAFG, BAFG bit.
Output timing between AAFG, BAFG bit and INTRB
AAFG（BAFG）bit
INTRB pin
Setting of the AAFG
Setting of the AAFG
（BAFG）
（BAFG）
（Matched alarm time（）Matched alarm time）（Matched alarm time）
Figure 22. Output timing between AAFG (BAFG) bit and INTRB
If time matching happened, AAFG (BAFG) bit will be kept high until it is set to “0”.
INTRB
Alarm-calendar coincidence
period (1 min.)
A
AALE←1 ^Day-of-the-
（BALE) ^{week, time}
matched
INTRB
AALE←0 AALE←1
（BALE） （BALE）
AALE←0 ^Day-of-the-
（BALE） ^{week, time}
matched
AALE←1 ^Day-of-the- AAFG←0
（BALE） ^{week, time} （BAFG）
matched
Day-of-the-
week, time
matched
Figure 23. Output timing between AALE (BALE) bit, AAFG (BAFG) bit and INTRB
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