BU9873 Datasheet, PDF (15/40 Pages) Rohm – I2C BUS Serial Interface RTC with High-precision Oscillation Adjustment

BU9873
Datasheet
2. Address Mapping of Internal Register
Internal address
A3 A2 A1 A0
00 0 0 0
Contents
Second Counter
Data
D7 D6
D5
D4
D3
D2
D1
D0
—
(Note1)
S₄₀
S₂₀
S₁₀
S₈
S₄
S₂
S₁
10 0 0 1
20 0 1 0
Minute Counter
Hour Counter
—
M₄₀
M₂₀
M₁₀
M₈
M₄
M₂
M₁
—
—
H₂₀
P/AB
H₁₀
H₈
H₄
H₂
H₁
3 0 0 1 1 Day-of-week Counter
—
—
—
—
—
W₄
W₂
W₁
40 1 0 0
Day Counter
—
—
D₂₀
D₁₀
D₈
D₄
D₂
D₁
50 1 0 1
Month Counter
—
—
—
MO₁₀ MO₈ MO₄ MO₂ MO₁
60 1 1 0
Year Counter
Y₈₀
Y₄₀
Y₂₀
Y₁₀
Y₈
Y₄
Y₂
Y₁
7 0 1 1 1 Time Trimming Register —
F₆
F₅
F₄
F₃
F₂
F₁
F₀
81 0 0 0
Alarm_A
(Minute Register)
— AM₄₀ AM₂₀ AM₁₀ AM₈ AM₄ AM₂ AM₁
91 0 0 1
Alarm_A
(Hour Register)
—
—
AH₂₀
AP/AB
AH₁₀
AH₈
AH₄
AH₂
AH₁
A1 0 1 0
Alarm_A
(Day-of-week Register)
— AW₆ AW₅ AW₄ AW₃ AW₂ AW₁ AW₀
B1 0 1 1
Alarm_B
(Minute Register)
— BM₄₀ BM₂₀ BM₁₀ BM₈ BM₄ BM₂ BM₁
C1 1 0 0
Alarm_B
(Hour Register)
—
—
BH₂₀
BP/AB
BH₁₀
BH₈
BH₄
BH₂
BH₁
D1 1 0 1
Alarm_B
(Day-of-week Register)
— BW₆ BW₅ BW4 BW₃ BW₂ BW₁ BW₀
E1 1 1 0
Control Register 1
AALE BALE —
—
TEST
(Note4)
CT₂
CT₁
CT₀
F1 1 1 1
Control Register 2
ADJ
(Note2)
—
— 12B/24 _XSTP CLENB CTFG AAFG BAFG
(Note3)
(Note1)
(Note2)
(Note3)
(Note4)
The “–” mark indicates data which can be read only and set to “0” when it is read.
For the ADJ/XSTP bit of control register 2, ADJ will be set to “1” if writing “1”, while XSTP will be set to “0” if writing “0” during normal oscillation.
Conversely, setting ADJ=0 and XSTP=1 cause no event. The value of XSTP bit is output when it is read.
When XSTP is set to “1”, the internal register F6 to F0, CT2 to CT0, AALE, BALE, CLENB will be reset to “0”.
The TEST bit of control register 1 is for shipment testing. Please always set TEST = 0. If this bit is set to “1” accidentally, it will be reset to “0” after stop
condition is input.
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13.Sep.2013 REV.001