RF5110G_07 Datasheet, PDF (4/22 Pages) RF Micro Devices – 3V GSM POWER AMPLIFIER

RF5110G
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pkg
Base
Function
VCC1
GND1
RF IN
GND2
VCC2
VCC2
NC
2F0
RF OUT
RF OUT
RF OUT
RF OUT
NC
VCC
APC2
APC1
GND
Description
Interface Schematic
Power supply for the pre-amplifier stage and interstage matching. This pin
forms the shunt inductance needed for proper tuning of the interstage
match. Refer to the application schematic for proper configuration. Note
that position and value of the components are important.
Ground connection for the pre-amplifier stage. Keep traces physically short
and connect immediately to the ground plane for best performance. It is
important for stability that this pin has it’s own vias to the groundplane, to
minimize any common inductance.
RF Input. This is a 50Ω input, but the actual impedance depends on the
interstage matching network connected to pin 1. An external DC blocking
capacitor is required if this port is connected to a DC path to ground or a
DC voltage.
See pin 3.
See pin 1.
VCC1
RF IN
From Bias
Stages ^GND1
Ground connection for the driver stage. To minimize the noise power at the
output, it is recommended to connect this pin with a trace of about 40mil
to the ground plane. This will slightly reduce the small signal gain, and
lower the noise power. It is important for stability that this pin have it’s own
vias to the ground plane, minimizing common inductance.
Power supply for the driver stage and interstage matching. This pin forms
the shunt inductance needed for proper tuning of the interstage match.
Please refer to the application schematic for proper configuration, and
note that position and value of the components are important.
Same as pin 5.
See pin 3.
VCC2
From Bias
Stages ^GND2
Not connected.
Connection for the second harmonic trap. This pin is internally connected
to the RF OUT pins. The bonding wire together with an external capacitor
form a series resonator that should be tuned to the second harmonic fre-
quency in order to increase efficiency and reduce spurious outputs.
RF Output and power supply for the output stage. Bias voltage for the final
stage is provided through this wide output pin. An external matching net-
work is required to provide the optimum load impedance.
Same as pin 9.
RF OUT
From Bias
Stages
GND
PCKG BASE
Same as pin 9.
Same as pin 9.
Same as pin 9.
Same as pin 9.
Same as pin 9.
Not connected.
Power supply for the bias circuits.
Power Control for the output stage. See pin 16 for more details.
See pin 16.
Power Control for the driver stage and pre-amplifier. When this pin is "low,"
all circuits are shut off. A "low" is typically 0.5V or less at room tempera-
ture. A shunt bypass capacitor is required. During normal operation this pin
is the power control. Control range varies from about 1.0V for -10dBm to
2.6V for +35dBm RF output power. The maximum power that can be
achieved depends on the actual output matching; see the application infor-
mation for more details. The maximum current into this pin is 5mA when
V_APC1=2.6V, and 0mA when V_APC=0V.
APC VCC
To RF
S ta g e s
Ground connection for the output stage. This pad should be connected to
the ground plane by vias directly under the device. A short path is required
to obtain optimum performance, as well as to provide a good thermal path
to the PCB for maximum heat dissipation.
GND
GND
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Rev A4 DS071026